1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s -check-prefixes=CHECK,GFX10 3# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1100 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s -check-prefixes=CHECK,GFX11 4 5v_log_f32 v0, v0 6v_rcp_f32 v0, v0 7v_rsq_f32 v1, v1 8v_sqrt_f32 v2, v0 9v_rcp_f64 v[0:1], v[0:1] 10v_rsq_f64 v[1:2], v[1:2] 11v_sqrt_f64 v[2:3], v[0:1] 12 13# CHECK: Iterations: 1 14# CHECK-NEXT: Instructions: 7 15 16# GFX10-NEXT: Total Cycles: 94 17# GFX11-NEXT: Total Cycles: 142 18 19# CHECK-NEXT: Total uOps: 7 20 21# CHECK: Dispatch Width: 1 22 23# GFX10-NEXT: uOps Per Cycle: 0.07 24# GFX10-NEXT: IPC: 0.07 25 26# GFX11-NEXT: uOps Per Cycle: 0.05 27# GFX11-NEXT: IPC: 0.05 28 29# CHECK-NEXT: Block RThroughput: 7.0 30 31# CHECK: Instruction Info: 32# CHECK-NEXT: [1]: #uOps 33# CHECK-NEXT: [2]: Latency 34# CHECK-NEXT: [3]: RThroughput 35# CHECK-NEXT: [4]: MayLoad 36# CHECK-NEXT: [5]: MayStore 37# CHECK-NEXT: [6]: HasSideEffects (U) 38 39# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 40# CHECK-NEXT: 1 10 1.00 U v_log_f32_e32 v0, v0 41# CHECK-NEXT: 1 10 1.00 U v_rcp_f32_e32 v0, v0 42# CHECK-NEXT: 1 10 1.00 U v_rsq_f32_e32 v1, v1 43# CHECK-NEXT: 1 10 1.00 U v_sqrt_f32_e32 v2, v0 44 45# GFX10-NEXT: 1 24 1.00 U v_rcp_f64_e32 v[0:1], v[0:1] 46# GFX10-NEXT: 1 24 1.00 U v_rsq_f64_e32 v[1:2], v[1:2] 47# GFX10-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1] 48 49# GFX11-NEXT: 1 40 1.00 U v_rcp_f64_e32 v[0:1], v[0:1] 50# GFX11-NEXT: 1 40 1.00 U v_rsq_f64_e32 v[1:2], v[1:2] 51# GFX11-NEXT: 1 40 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1] 52 53# CHECK: Resources: 54# CHECK-NEXT: [0] - HWBranch 55# CHECK-NEXT: [1] - HWExport 56# CHECK-NEXT: [2] - HWLGKM 57# CHECK-NEXT: [3] - HWRC 58# CHECK-NEXT: [4] - HWSALU 59# CHECK-NEXT: [5] - HWTransVALU 60# CHECK-NEXT: [6] - HWVALU 61# CHECK-NEXT: [7] - HWVMEM 62 63# CHECK: Resource pressure per iteration: 64# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] 65# CHECK-NEXT: - - - 7.00 - 7.00 3.00 - 66 67# CHECK: Resource pressure by instruction: 68# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: 69# CHECK-NEXT: - - - 1.00 - 1.00 - - v_log_f32_e32 v0, v0 70# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0 71# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1 72# CHECK-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0 73# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1] 74# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2] 75# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1] 76 77# CHECK: Timeline view: 78 79# GFX10-NEXT: 0123456789 0123456789 0123456789 0123456789 0123 80# GFX10-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 81 82# GFX11-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 83# GFX11-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 01 84 85# GFX10: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . v_log_f32_e32 v0, v0 86# GFX10-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . v_rcp_f32_e32 v0, v0 87# GFX10-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . v_rsq_f32_e32 v1, v1 88# GFX10-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . v_sqrt_f32_e32 v2, v0 89# GFX10-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_rcp_f64_e32 v[0:1], v[0:1] 90# GFX10-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. . . . . . v_rsq_f64_e32 v[1:2], v[1:2] 91# GFX10-NEXT: [0,6] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1] 92 93# GFX11: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . .. v_log_f32_e32 v0, v0 94# GFX11-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . .. v_rcp_f32_e32 v0, v0 95# GFX11-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . .. v_rsq_f32_e32 v1, v1 96# GFX11-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . .. v_sqrt_f32_e32 v2, v0 97# GFX11-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . .. v_rcp_f64_e32 v[0:1], v[0:1] 98# GFX11-NEXT: [0,5] . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . .. v_rsq_f64_e32 v[1:2], v[1:2] 99# GFX11-NEXT: [0,6] . . . . . . . . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1] 100 101# CHECK: Average Wait times (based on the timeline view): 102# CHECK-NEXT: [0]: Executions 103# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 104# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 105# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 106 107# CHECK: [0] [1] [2] [3] 108# CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_log_f32_e32 v0, v0 109# CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_rcp_f32_e32 v0, v0 110# CHECK-NEXT: 2. 1 0.0 0.0 0.0 v_rsq_f32_e32 v1, v1 111# CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_sqrt_f32_e32 v2, v0 112# CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_rcp_f64_e32 v[0:1], v[0:1] 113# CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_rsq_f64_e32 v[1:2], v[1:2] 114# CHECK-NEXT: 6. 1 0.0 0.0 0.0 v_sqrt_f64_e32 v[2:3], v[0:1] 115# CHECK-NEXT: 1 0.0 0.0 0.0 <total> 116