1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6fmov d31, #1.00000000 7fdiv d30, d31, d30 8 9# Newton series for 1 / x. 10frecpe d1, d0 11frecps d2, d0, d1 12fmul d1, d1, d2 13frecps d2, d0, d1 14fmul d1, d1, d2 15frecps d0, d0, d1 16fmul d0, d1, d0 17 18# ALL: Iterations: 100 19# ALL-NEXT: Instructions: 900 20 21# M3-NEXT: Total Cycles: 2503 22# M4-NEXT: Total Cycles: 2403 23# M5-NEXT: Total Cycles: 2403 24 25# ALL-NEXT: Total uOps: 900 26 27# ALL: Dispatch Width: 6 28 29# M3-NEXT: uOps Per Cycle: 0.36 30# M3-NEXT: IPC: 0.36 31# M3-NEXT: Block RThroughput: 3.3 32 33# M4-NEXT: uOps Per Cycle: 0.37 34# M4-NEXT: IPC: 0.37 35# M4-NEXT: Block RThroughput: 2.3 36 37# M5-NEXT: uOps Per Cycle: 0.37 38# M5-NEXT: IPC: 0.37 39# M5-NEXT: Block RThroughput: 2.3 40 41# ALL: Instruction Info: 42# ALL-NEXT: [1]: #uOps 43# ALL-NEXT: [2]: Latency 44# ALL-NEXT: [3]: RThroughput 45# ALL-NEXT: [4]: MayLoad 46# ALL-NEXT: [5]: MayStore 47# ALL-NEXT: [6]: HasSideEffects (U) 48 49# ALL: [1] [2] [3] [4] [5] [6] Instructions: 50# ALL-NEXT: 1 1 0.33 fmov d31, #1.00000000 51 52# M3-NEXT: 1 12 3.25 fdiv d30, d31, d30 53# M3-NEXT: 1 4 0.50 frecpe d1, d0 54 55# M4-NEXT: 1 12 2.25 fdiv d30, d31, d30 56# M4-NEXT: 1 3 0.50 frecpe d1, d0 57 58# M5-NEXT: 1 12 2.25 fdiv d30, d31, d30 59# M5-NEXT: 1 3 0.50 frecpe d1, d0 60 61# ALL-NEXT: 1 4 0.33 frecps d2, d0, d1 62# ALL-NEXT: 1 3 0.33 fmul d1, d1, d2 63# ALL-NEXT: 1 4 0.33 frecps d2, d0, d1 64# ALL-NEXT: 1 3 0.33 fmul d1, d1, d2 65# ALL-NEXT: 1 4 0.33 frecps d0, d0, d1 66# ALL-NEXT: 1 3 0.33 fmul d0, d1, d0 67