1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s 3 4fdiv s1, s2, s3 5add w8, w8, #1 6add w1, w2, w0 7add w3, w4, #1 8add w5, w6, w0 9add w7, w9, w0 10 11# CHECK: Iterations: 2 12# CHECK-NEXT: Instructions: 12 13# CHECK-NEXT: Total Cycles: 24 14# CHECK-NEXT: Total uOps: 12 15 16# CHECK: Dispatch Width: 2 17# CHECK-NEXT: uOps Per Cycle: 0.50 18# CHECK-NEXT: IPC: 0.50 19# CHECK-NEXT: Block RThroughput: 10.0 20 21# CHECK: Instruction Info: 22# CHECK-NEXT: [1]: #uOps 23# CHECK-NEXT: [2]: Latency 24# CHECK-NEXT: [3]: RThroughput 25# CHECK-NEXT: [4]: MayLoad 26# CHECK-NEXT: [5]: MayStore 27# CHECK-NEXT: [6]: HasSideEffects (U) 28 29# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 30# CHECK-NEXT: 1 13 10.00 fdiv s1, s2, s3 31# CHECK-NEXT: 1 3 0.50 add w8, w8, #1 32# CHECK-NEXT: 1 3 0.50 add w1, w2, w0 33# CHECK-NEXT: 1 3 0.50 add w3, w4, #1 34# CHECK-NEXT: 1 3 0.50 add w5, w6, w0 35# CHECK-NEXT: 1 3 0.50 add w7, w9, w0 36 37# CHECK: Dynamic Dispatch Stall Cycles: 38# CHECK-NEXT: RAT - Register unavailable: 0 39# CHECK-NEXT: RCU - Retire tokens unavailable: 0 40# CHECK-NEXT: SCHEDQ - Scheduler full: 0 41# CHECK-NEXT: LQ - Load queue full: 0 42# CHECK-NEXT: SQ - Store queue full: 0 43# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 7 (29.2%) 44# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 45 46# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 47# CHECK-NEXT: [# dispatched], [# cycles] 48# CHECK-NEXT: 0, 18 (75.0%) 49# CHECK-NEXT: 2, 6 (25.0%) 50 51# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 52# CHECK-NEXT: [# issued], [# cycles] 53# CHECK-NEXT: 0, 18 (75.0%) 54# CHECK-NEXT: 2, 6 (25.0%) 55 56# CHECK: Scheduler's queue usage: 57# CHECK-NEXT: No scheduler resources used. 58 59# CHECK: Register File statistics: 60# CHECK-NEXT: Total number of mappings created: 12 61# CHECK-NEXT: Max number of mappings used: 7 62 63# CHECK: Resources: 64# CHECK-NEXT: [0.0] - CortexA55UnitALU 65# CHECK-NEXT: [0.1] - CortexA55UnitALU 66# CHECK-NEXT: [1] - CortexA55UnitB 67# CHECK-NEXT: [2] - CortexA55UnitDiv 68# CHECK-NEXT: [3.0] - CortexA55UnitFPALU 69# CHECK-NEXT: [3.1] - CortexA55UnitFPALU 70# CHECK-NEXT: [4] - CortexA55UnitFPDIV 71# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC 72# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC 73# CHECK-NEXT: [6] - CortexA55UnitLd 74# CHECK-NEXT: [7] - CortexA55UnitMAC 75# CHECK-NEXT: [8] - CortexA55UnitSt 76 77# CHECK: Resource pressure per iteration: 78# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] 79# CHECK-NEXT: 2.50 2.50 - - - - 10.00 - - - - - 80 81# CHECK: Resource pressure by instruction: 82# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions: 83# CHECK-NEXT: - - - - - - 10.00 - - - - - fdiv s1, s2, s3 84# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w8, w8, #1 85# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w1, w2, w0 86# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w3, w4, #1 87# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w5, w6, w0 88# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w7, w9, w0 89 90# CHECK: Timeline view: 91# CHECK-NEXT: 0123456789 92# CHECK-NEXT: Index 0123456789 0123 93 94# CHECK: [0,0] DeeeeeeeeeeeeE . . . fdiv s1, s2, s3 95# CHECK-NEXT: [0,1] DeeE . . . . . add w8, w8, #1 96# CHECK-NEXT: [0,2] .DeeE. . . . . add w1, w2, w0 97# CHECK-NEXT: [0,3] .DeeE. . . . . add w3, w4, #1 98# CHECK-NEXT: [0,4] . DeeE . . . . add w5, w6, w0 99# CHECK-NEXT: [0,5] . DeeE . . . . add w7, w9, w0 100# CHECK-NEXT: [1,0] . . DeeeeeeeeeeeeE fdiv s1, s2, s3 101# CHECK-NEXT: [1,1] . . DeeE . . . add w8, w8, #1 102# CHECK-NEXT: [1,2] . . .DeeE. . . add w1, w2, w0 103# CHECK-NEXT: [1,3] . . .DeeE. . . add w3, w4, #1 104# CHECK-NEXT: [1,4] . . . DeeE . . add w5, w6, w0 105# CHECK-NEXT: [1,5] . . . DeeE . . add w7, w9, w0 106 107# CHECK: Average Wait times (based on the timeline view): 108# CHECK-NEXT: [0]: Executions 109# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 110# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 111# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 112 113# CHECK: [0] [1] [2] [3] 114# CHECK-NEXT: 0. 2 0.0 0.0 0.0 fdiv s1, s2, s3 115# CHECK-NEXT: 1. 2 0.0 0.0 0.0 add w8, w8, #1 116# CHECK-NEXT: 2. 2 0.0 0.0 0.0 add w1, w2, w0 117# CHECK-NEXT: 3. 2 0.0 0.0 0.0 add w3, w4, #1 118# CHECK-NEXT: 4. 2 0.0 0.0 0.0 add w5, w6, w0 119# CHECK-NEXT: 5. 2 0.0 0.0 0.0 add w7, w9, w0 120# CHECK-NEXT: 2 0.0 0.0 0.0 <total> 121