1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=3 -noalias=false < %s | FileCheck %s 3 4# PR50483: Execution of loads and stores should not overlap if flag -noalias is set to false. 5 6str x1, [x10] 7str x1, [x10] 8ldr x2, [x10] 9nop 10ldr x2, [x10] 11ldr x3, [x10] 12 13# CHECK: Iterations: 3 14# CHECK-NEXT: Instructions: 18 15# CHECK-NEXT: Total Cycles: 31 16# CHECK-NEXT: Total uOps: 18 17 18# CHECK: Dispatch Width: 2 19# CHECK-NEXT: uOps Per Cycle: 0.58 20# CHECK-NEXT: IPC: 0.58 21# CHECK-NEXT: Block RThroughput: 3.0 22 23# CHECK: Instruction Info: 24# CHECK-NEXT: [1]: #uOps 25# CHECK-NEXT: [2]: Latency 26# CHECK-NEXT: [3]: RThroughput 27# CHECK-NEXT: [4]: MayLoad 28# CHECK-NEXT: [5]: MayStore 29# CHECK-NEXT: [6]: HasSideEffects (U) 30 31# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 32# CHECK-NEXT: 1 1 1.00 * str x1, [x10] 33# CHECK-NEXT: 1 1 1.00 * str x1, [x10] 34# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10] 35# CHECK-NEXT: 1 1 1.00 * * U nop 36# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10] 37# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10] 38 39# CHECK: Resources: 40# CHECK-NEXT: [0.0] - CortexA55UnitALU 41# CHECK-NEXT: [0.1] - CortexA55UnitALU 42# CHECK-NEXT: [1] - CortexA55UnitB 43# CHECK-NEXT: [2] - CortexA55UnitDiv 44# CHECK-NEXT: [3.0] - CortexA55UnitFPALU 45# CHECK-NEXT: [3.1] - CortexA55UnitFPALU 46# CHECK-NEXT: [4] - CortexA55UnitFPDIV 47# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC 48# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC 49# CHECK-NEXT: [6] - CortexA55UnitLd 50# CHECK-NEXT: [7] - CortexA55UnitMAC 51# CHECK-NEXT: [8] - CortexA55UnitSt 52 53# CHECK: Resource pressure per iteration: 54# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] 55# CHECK-NEXT: - - 1.00 - - - - - - 3.00 - 2.00 56 57# CHECK: Resource pressure by instruction: 58# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions: 59# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10] 60# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10] 61# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10] 62# CHECK-NEXT: - - 1.00 - - - - - - - - - nop 63# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10] 64# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10] 65 66# CHECK: Timeline view: 67# CHECK-NEXT: 0123456789 0 68# CHECK-NEXT: Index 0123456789 0123456789 69 70# CHECK: [0,0] DE . . . . . . str x1, [x10] 71# CHECK-NEXT: [0,1] .DE . . . . . . str x1, [x10] 72# CHECK-NEXT: [0,2] . DeeE . . . . . ldr x2, [x10] 73# CHECK-NEXT: [0,3] . DE . . . . . nop 74# CHECK-NEXT: [0,4] . .DeeE. . . . . ldr x2, [x10] 75# CHECK-NEXT: [0,5] . . DeeE . . . . ldr x3, [x10] 76# CHECK-NEXT: [1,0] . . DE . . . . str x1, [x10] 77# CHECK-NEXT: [1,1] . . .DE . . . . str x1, [x10] 78# CHECK-NEXT: [1,2] . . . DeeE . . . ldr x2, [x10] 79# CHECK-NEXT: [1,3] . . . DE . . . nop 80# CHECK-NEXT: [1,4] . . . .DeeE. . . ldr x2, [x10] 81# CHECK-NEXT: [1,5] . . . . DeeE . . ldr x3, [x10] 82# CHECK-NEXT: [2,0] . . . . DE . . str x1, [x10] 83# CHECK-NEXT: [2,1] . . . . .DE . . str x1, [x10] 84# CHECK-NEXT: [2,2] . . . . . DeeE . ldr x2, [x10] 85# CHECK-NEXT: [2,3] . . . . . DE . nop 86# CHECK-NEXT: [2,4] . . . . . .DeeE. ldr x2, [x10] 87# CHECK-NEXT: [2,5] . . . . . . DeeE ldr x3, [x10] 88 89# CHECK: Average Wait times (based on the timeline view): 90# CHECK-NEXT: [0]: Executions 91# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 92# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 93# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 94 95# CHECK: [0] [1] [2] [3] 96# CHECK-NEXT: 0. 3 0.0 0.0 0.0 str x1, [x10] 97# CHECK-NEXT: 1. 3 0.0 0.0 0.0 str x1, [x10] 98# CHECK-NEXT: 2. 3 0.0 0.0 0.0 ldr x2, [x10] 99# CHECK-NEXT: 3. 3 0.0 0.0 0.0 nop 100# CHECK-NEXT: 4. 3 0.0 0.0 0.0 ldr x2, [x10] 101# CHECK-NEXT: 5. 3 0.0 0.0 0.0 ldr x3, [x10] 102# CHECK-NEXT: 3 0.0 0.0 0.0 <total> 103