1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;; Check that we remove the exact MCInst number from --asm-verbose output
3; RUN: llc < %s -mtriple=i686-unknown-unknown --asm-show-inst | FileCheck %s --check-prefix=VERBOSE
4; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=CHECK
5
6define i8 @add_i8(i8 %a) nounwind {
7; VERBOSE-LABEL: add_i8:
8; VERBOSE:       # %bb.0:
9; VERBOSE-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # <MCInst #[[#MCINST1:]] MOVZX32rm8
10; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
11; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>
12; VERBOSE-NEXT:    # <MCOperand Imm:1>
13; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>
14; VERBOSE-NEXT:    # <MCOperand Imm:4>
15; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
16; VERBOSE-NEXT:    addb $2, %al # <MCInst #[[#MCINST2:]] ADD8i8
17; VERBOSE-NEXT:    # <MCOperand Imm:2>>
18; VERBOSE-NEXT:    retl # <MCInst #[[#MCINST3:]] RET32
19; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>>
20;
21; CHECK-LABEL: add_i8:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
24; CHECK-NEXT:    addb $2, %al
25; CHECK-NEXT:    retl
26  %add = add i8 %a, 2
27  ret i8 %add
28}
29
30define i32 @add_i32(i32 %a) nounwind {
31; VERBOSE-LABEL: add_i32:
32; VERBOSE:       # %bb.0:
33; VERBOSE-NEXT:    movl {{[0-9]+}}(%esp), %eax # <MCInst #[[#MCINST4:]] MOV32rm
34; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
35; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG2]]>
36; VERBOSE-NEXT:    # <MCOperand Imm:1>
37; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
38; VERBOSE-NEXT:    # <MCOperand Imm:4>
39; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
40; VERBOSE-NEXT:    addl $2, %eax # <MCInst #[[#MCINST5:]] ADD32ri8
41; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
42; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
43; VERBOSE-NEXT:    # <MCOperand Imm:2>>
44; VERBOSE-NEXT:    retl # <MCInst #[[#MCINST3]] RET32
45; VERBOSE-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
46;
47; CHECK-LABEL: add_i32:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
50; CHECK-NEXT:    addl $2, %eax
51; CHECK-NEXT:    retl
52  %add = add i32 %a, 2
53  ret i32 %add
54}
55