1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s 3 4define i64 @i64_test(i64 %i) nounwind readnone { 5; CHECK-LABEL: i64_test: 6; CHECK: SelectionDAG has 25 nodes: 7; CHECK-NEXT: t0: ch,glue = EntryToken 8; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8 9; CHECK-NEXT: t4: i32,ch = CopyFromReg # D:1 t0, Register:i32 %9 10; CHECK-NEXT: t49: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<60>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11> 11; CHECK-NEXT: t26: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0 12; CHECK-NEXT: t29: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0 13; CHECK-NEXT: t32: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<60>, t26, TargetConstant:i32<3>, t29, TargetConstant:i32<11> 14; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t49, t32 15; CHECK-NEXT: t23: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3> 16; CHECK-NEXT: t16: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t23 17; CHECK-NEXT: t38: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11> 18; CHECK-NEXT: t18: ch,glue = CopyToReg # D:1 t16, Register:i32 $vgpr1, t38, t16:1 19; CHECK-NEXT: t19: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t18, t18:1 20; CHECK-EMPTY: 21 %loc = alloca i64, addrspace(5) 22 %j = load i64, ptr addrspace(5) %loc 23 %r = add i64 %i, %j 24 ret i64 %r 25} 26 27define i64 @i32_test(i32 %i) nounwind readnone { 28; CHECK-LABEL: i32_test: 29; CHECK: SelectionDAG has 15 nodes: 30; CHECK-NEXT: t0: ch,glue = EntryToken 31; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8 32; CHECK-NEXT: t6: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0 33; CHECK-NEXT: t7: i32,i1 = V_ADD_CO_U32_e64 # D:1 t2, t6, TargetConstant:i1<0> 34; CHECK-NEXT: t14: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t7 35; CHECK-NEXT: t22: i32 = V_MOV_B32_e32 TargetConstant:i32<0> 36; CHECK-NEXT: t16: ch,glue = CopyToReg t14, Register:i32 $vgpr1, t22, t14:1 37; CHECK-NEXT: t17: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t16, t16:1 38; CHECK-EMPTY: 39 %loc = alloca i32, addrspace(5) 40 %j = load i32, ptr addrspace(5) %loc 41 %r = add i32 %i, %j 42 %ext = zext i32 %r to i64 43 ret i64 %ext 44} 45 46define i64 @i16_test(i16 %i) nounwind readnone { 47; CHECK-LABEL: i16_test: 48; CHECK: SelectionDAG has 18 nodes: 49; CHECK-NEXT: t0: ch,glue = EntryToken 50; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8 51; CHECK-NEXT: t19: i32,ch = BUFFER_LOAD_USHORT_OFFEN<Mem:(dereferenceable load (s16) from %ir.loc, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0 52; CHECK-NEXT: t20: i32,i1 = V_ADD_CO_U32_e64 # D:1 t2, t19, TargetConstant:i1<0> 53; CHECK-NEXT: t24: i32 = S_MOV_B32 TargetConstant:i32<65535> 54; CHECK-NEXT: t25: i32 = V_AND_B32_e64 # D:1 t20, t24 55; CHECK-NEXT: t15: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t25 56; CHECK-NEXT: t31: i32 = V_MOV_B32_e32 TargetConstant:i32<0> 57; CHECK-NEXT: t17: ch,glue = CopyToReg t15, Register:i32 $vgpr1, t31, t15:1 58; CHECK-NEXT: t18: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t17, t17:1 59; CHECK-EMPTY: 60 %loc = alloca i16, addrspace(5) 61 %j = load i16, ptr addrspace(5) %loc 62 %r = add i16 %i, %j 63 %ext = zext i16 %r to i64 64 ret i64 %ext 65} 66 67define i64 @i8_test(i8 %i) nounwind readnone { 68; CHECK-LABEL: i8_test: 69; CHECK: SelectionDAG has 18 nodes: 70; CHECK-NEXT: t0: ch,glue = EntryToken 71; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8 72; CHECK-NEXT: t19: i32,ch = BUFFER_LOAD_UBYTE_OFFEN<Mem:(dereferenceable load (s8) from %ir.loc, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0 73; CHECK-NEXT: t20: i32,i1 = V_ADD_CO_U32_e64 # D:1 t2, t19, TargetConstant:i1<0> 74; CHECK-NEXT: t24: i32 = S_MOV_B32 TargetConstant:i32<255> 75; CHECK-NEXT: t25: i32 = V_AND_B32_e64 # D:1 t20, t24 76; CHECK-NEXT: t15: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t25 77; CHECK-NEXT: t31: i32 = V_MOV_B32_e32 TargetConstant:i32<0> 78; CHECK-NEXT: t17: ch,glue = CopyToReg t15, Register:i32 $vgpr1, t31, t15:1 79; CHECK-NEXT: t18: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t17, t17:1 80; CHECK-EMPTY: 81 %loc = alloca i8, addrspace(5) 82 %j = load i8, ptr addrspace(5) %loc 83 %r = add i8 %i, %j 84 %ext = zext i8 %r to i64 85 ret i64 %ext 86} 87