1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=mem2reg,simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s 3 4define i32 @test_inline_constraint_S_label_tailmerged(i1 %in) { 5; CHECK-LABEL: @test_inline_constraint_S_label_tailmerged( 6; CHECK-NEXT: call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, [[COMMON_RET:%.*]])) 7; CHECK-NEXT: [[COMMON_RETVAL:%.*]] = select i1 [[IN:%.*]], i32 0, i32 42 8; CHECK-NEXT: br label [[COMMON_RET]] 9; CHECK: common.ret: 10; CHECK-NEXT: ret i32 [[COMMON_RETVAL]] 11; 12 call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, %loc)) 13 br i1 %in, label %loc, label %loc2 14loc: 15 br label %common.ret 16loc2: 17 br label %common.ret 18common.ret: 19 %common.retval = phi i32 [ 0, %loc ], [ 42, %loc2 ] 20 ret i32 %common.retval 21} 22 23define i32 @test_inline_constraint_S_label_tailmerged2(i1 %in) { 24; CHECK-LABEL: @test_inline_constraint_S_label_tailmerged2( 25; CHECK-NEXT: common.ret: 26; CHECK-NEXT: call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, [[COMMON_RET:%.*]])) 27; CHECK-NEXT: [[DOT:%.*]] = select i1 [[IN:%.*]], i32 0, i32 42 28; CHECK-NEXT: ret i32 [[DOT]] 29; 30 call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, %loc)) 31 br i1 %in, label %loc, label %loc2 32common.ret: 33 %common.retval = phi i32 [ 0, %loc ], [ 42, %loc2 ] 34 ret i32 %common.retval 35loc: 36 br label %common.ret 37loc2: 38 br label %common.ret 39} 40