1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE 3; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE 4; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE 5 6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 7target triple = "hexagon-unknown--elf" 8 9; Function Attrs: noinline nounwind 10define i32 @foo(i32 %x) #0 section ".tcm_text" { 11; ENABLE-LABEL: @foo( 12; ENABLE-NEXT: entry: 13; ENABLE-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 6 14; ENABLE-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] 15; ENABLE: switch.lookup: 16; ENABLE-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds nuw [6 x i32], ptr @switch.table.foo, i32 0, i32 [[X]] 17; ENABLE-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 18; ENABLE-NEXT: br label [[RETURN]] 19; ENABLE: return: 20; ENABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 19, [[ENTRY:%.*]] ] 21; ENABLE-NEXT: ret i32 [[RETVAL_0]] 22; 23; DISABLE-LABEL: @foo( 24; DISABLE-NEXT: entry: 25; DISABLE-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [ 26; DISABLE-NEXT: i32 0, label [[RETURN:%.*]] 27; DISABLE-NEXT: i32 1, label [[SW_BB1:%.*]] 28; DISABLE-NEXT: i32 2, label [[SW_BB2:%.*]] 29; DISABLE-NEXT: i32 3, label [[SW_BB3:%.*]] 30; DISABLE-NEXT: i32 4, label [[SW_BB4:%.*]] 31; DISABLE-NEXT: i32 5, label [[SW_BB5:%.*]] 32; DISABLE-NEXT: ] 33; DISABLE: sw.bb1: 34; DISABLE-NEXT: br label [[RETURN]] 35; DISABLE: sw.bb2: 36; DISABLE-NEXT: br label [[RETURN]] 37; DISABLE: sw.bb3: 38; DISABLE-NEXT: br label [[RETURN]] 39; DISABLE: sw.bb4: 40; DISABLE-NEXT: br label [[RETURN]] 41; DISABLE: sw.bb5: 42; DISABLE-NEXT: br label [[RETURN]] 43; DISABLE: sw.default: 44; DISABLE-NEXT: br label [[RETURN]] 45; DISABLE: return: 46; DISABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 19, [[SW_DEFAULT]] ], [ 33, [[SW_BB5]] ], [ 12, [[SW_BB4]] ], [ 22, [[SW_BB3]] ], [ 14, [[SW_BB2]] ], [ 20, [[SW_BB1]] ], [ 9, [[ENTRY:%.*]] ] 47; DISABLE-NEXT: ret i32 [[RETVAL_0]] 48; 49entry: 50 %retval = alloca i32, align 4 51 %x.addr = alloca i32, align 4 52 store i32 %x, ptr %x.addr, align 4 53 %0 = load i32, ptr %x.addr, align 4 54 switch i32 %0, label %sw.default [ 55 i32 0, label %sw.bb 56 i32 1, label %sw.bb1 57 i32 2, label %sw.bb2 58 i32 3, label %sw.bb3 59 i32 4, label %sw.bb4 60 i32 5, label %sw.bb5 61 ] 62 63sw.bb: ; preds = %entry 64 store i32 9, ptr %retval, align 4 65 br label %return 66 67sw.bb1: ; preds = %entry 68 store i32 20, ptr %retval, align 4 69 br label %return 70 71sw.bb2: ; preds = %entry 72 store i32 14, ptr %retval, align 4 73 br label %return 74 75sw.bb3: ; preds = %entry 76 store i32 22, ptr %retval, align 4 77 br label %return 78 79sw.bb4: ; preds = %entry 80 store i32 12, ptr %retval, align 4 81 br label %return 82 83sw.bb5: ; preds = %entry 84 store i32 33, ptr %retval, align 4 85 br label %return 86 87sw.default: ; preds = %entry 88 store i32 19, ptr %retval, align 4 89 br label %return 90 91return: ; preds = %sw.default, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb 92 %1 = load i32, ptr %retval, align 4 93 ret i32 %1 94} 95 96attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } 97