1; REQUIRES: x86_64-linux 2; RUN: opt < %s -passes='pseudo-probe,jump-threading' -S -o %t 3; RUN: FileCheck %s < %t --check-prefix=JT 4; RUN: llc -function-sections <%t -filetype=asm | FileCheck %s --check-prefix=ASM 5; RUN: opt < %s -passes='pseudo-probe' -S -o %t1 6; RUN: llc -stop-after=tailduplication <%t1 | FileCheck %s --check-prefix=MIR-tail 7; RUN: opt < %s -passes='pseudo-probe,simplifycfg' -S | FileCheck %s --check-prefix=SC 8 9declare i32 @f1() 10 11define i32 @foo(i1 %cond) { 12; JT-LABEL: @foo( 13; JT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 1, i32 0, i64 -1) 14; ASM: pseudoprobe 6699318081062747564 1 0 0 15 %call = call i32 @f1() 16 br i1 %cond, label %T, label %F 17T: 18 br label %Merge 19F: 20 br label %Merge 21Merge: 22;; Check branch T and F are gone, and their probes (probe 2 and 3) are gone too. 23; JT-LABEL-NO: T 24; JT-LABEL-NO: F 25; JT-LABEL: Merge 26; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 4 27; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 3 28; JT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 5, i32 0, i64 -1) 29; ASM-NOT: .pseudoprobe 6699318081062747564 4 30; ASM-NOT: .pseudoprobe 6699318081062747564 3 31; ASM: .pseudoprobe 6699318081062747564 5 0 0 32 ret i32 %call 33} 34 35;; Check block T and F are gone, and their probes (probe 2 and 3) are gone too. 36; MIR-tail: bb.0 37; MIR-tail: PSEUDO_PROBE [[#GUID:]], 1, 0, 0 38; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 3 39; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 4 40; MIR-tail: PSEUDO_PROBE [[#GUID:]], 5, 0, 0 41 42 43define i32 @test(i32 %a, i32 %b, i32 %c) { 44;; Check block bb1 and bb2 are gone, and their probes (probe 2 and 3) are gone too. 45; SC-LABEL: @test( 46; SC-LABEL-NO: bb1 47; SC-LABEL-NO: bb2 48; SC: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0 49; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 2 50; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 3 51; SC: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 1 52; SC: [[T3:%.*]] = add i32 [[A:%.*]], 1 53; SC: [[SPEC_SELECT:%.*]] = select i1 [[T2]], i32 [[T3]], i32 [[A]] 54; SC: [[T4:%.*]] = select i1 [[T1]], i32 [[SPEC_SELECT]], i32 [[B]] 55; SC: [[T5:%.*]] = sub i32 [[T4]], 1 56; SC: ret i32 [[T5]] 57 58entry: 59 %t1 = icmp eq i32 %b, 0 60 br i1 %t1, label %bb1, label %bb3 61 62bb1: 63 %t2 = icmp sgt i32 %c, 1 64 br i1 %t2, label %bb2, label %bb3 65 66bb2: 67 %t3 = add i32 %a, 1 68 br label %bb3 69 70bb3: 71 %t4 = phi i32 [ %b, %entry ], [ %a, %bb1 ], [ %t3, %bb2 ] 72 %t5 = sub i32 %t4, 1 73 ret i32 %t5 74} 75