xref: /llvm-project/llvm/test/Transforms/SROA/irregular-type.ll (revision 4f7e5d22060e8a89237ffb93c3e7be6e92fee8fe)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
4
5%S = type { [4 x i8] }
6
7; Ensure the load/store of integer types whose size is not equal to the store
8; size are not split.
9
10define i8 @foo(i23 %0) {
11; CHECK-LABEL: @foo(
12; CHECK-NEXT:  Entry:
13; CHECK-NEXT:    [[DOTSROA_0:%.*]] = alloca [3 x i8], align 8
14; CHECK-NEXT:    store i23 [[TMP0:%.*]], ptr [[DOTSROA_0]], align 8
15; CHECK-NEXT:    [[DOTSROA_0_1__SROA_IDX1:%.*]] = getelementptr inbounds i8, ptr [[DOTSROA_0]], i64 1
16; CHECK-NEXT:    [[DOTSROA_0_1__SROA_0_1_:%.*]] = load i8, ptr [[DOTSROA_0_1__SROA_IDX1]], align 1
17; CHECK-NEXT:    ret i8 [[DOTSROA_0_1__SROA_0_1_]]
18;
19Entry:
20  %1 = alloca %S
21  store i23 %0, ptr %1
22  %2 = getelementptr inbounds %S, ptr %1, i64 0, i32 0, i32 1
23  %3 = load i8, ptr %2
24  ret i8 %3
25}
26
27define i32 @bar(i16 %0) {
28; CHECK-LABEL: @bar(
29; CHECK-NEXT:  Entry:
30; CHECK-NEXT:    [[DOTSROA_0:%.*]] = alloca [3 x i8], align 8
31; CHECK-NEXT:    store i16 [[TMP0:%.*]], ptr [[DOTSROA_0]], align 8
32; CHECK-NEXT:    [[DOTSROA_0_0__SROA_0_0_:%.*]] = load i17, ptr [[DOTSROA_0]], align 8
33; CHECK-NEXT:    [[TMP1:%.*]] = zext i17 [[DOTSROA_0_0__SROA_0_0_]] to i32
34; CHECK-NEXT:    ret i32 [[TMP1]]
35;
36Entry:
37  %1 = alloca %S
38  store i16 %0, ptr %1
39  %2 = load i17, ptr %1
40  %3 = zext i17 %2 to i32
41  ret i32 %3
42}
43;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
44; CHECK-MODIFY-CFG: {{.*}}
45; CHECK-PRESERVE-CFG: {{.*}}
46