1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4 5define i32 @test(i32 %a, i8 %b, i8 %c) { 6; CHECK-LABEL: define i32 @test( 7; CHECK-SAME: i32 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) { 8; CHECK-NEXT: entry: 9; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i32 0 10; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer 11; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], <i8 -1, i8 -2, i8 -3, i8 -4> 12; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 0 13; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer 14; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16> 15; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i8> [[TMP4]] to <4 x i16> 16; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <4 x i16> [[TMP8]], [[TMP9]] 17; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i1> [[TMP5]] to i4 18; CHECK-NEXT: [[TMP11:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP10]]) 19; CHECK-NEXT: [[TMP7:%.*]] = zext i4 [[TMP11]] to i32 20; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP7]], [[A]] 21; CHECK-NEXT: ret i32 [[OP_RDX]] 22; 23entry: 24 %0 = add i8 %c, -3 25 %dec19 = add i8 %c, -1 26 %conv20 = zext i8 %dec19 to i32 27 %conv16.1 = sext i8 %b to i32 28 %cmp17.1 = icmp sle i32 %conv20, %conv16.1 29 %conv18.1 = zext i1 %cmp17.1 to i32 30 %a.1 = add nsw i32 %conv18.1, %a 31 %dec19.1 = add i8 %c, -2 32 %conv20.1 = zext i8 %dec19.1 to i32 33 %conv16.2 = sext i8 %b to i32 34 %cmp17.2 = icmp sle i32 %conv20.1, %conv16.2 35 %conv18.2 = zext i1 %cmp17.2 to i32 36 %a.2 = add nsw i32 %a.1, %conv18.2 37 %1 = zext i8 %0 to i32 38 %conv16.158 = sext i8 %b to i32 39 %cmp17.159 = icmp sle i32 %1, %conv16.158 40 %conv18.160 = zext i1 %cmp17.159 to i32 41 %a.161 = add nsw i32 %a.2, %conv18.160 42 %dec19.162 = add i8 %c, -4 43 %conv20.163 = zext i8 %dec19.162 to i32 44 %conv16.1.1 = sext i8 %b to i32 45 %cmp17.1.1 = icmp sle i32 %conv20.163, %conv16.1.1 46 %conv18.1.1 = zext i1 %cmp17.1.1 to i32 47 %a.1.1 = add nsw i32 %a.161, %conv18.1.1 48 ret i32 %a.1.1 49} 50 51