1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: %if x86-registered-target %{ opt < %s -passes=slp-vectorizer -slp-revec -mtriple=x86_64 -S | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt < %s -passes=slp-vectorizer -slp-revec -mtriple=aarch64-unknown-linux-gnu -S | FileCheck %s %} 4 5define i1 @logical_and_icmp_diff_preds(<4 x i32> %x) { 6; CHECK-LABEL: @logical_and_icmp_diff_preds( 7; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, <4 x i32> <i32 1, i32 3, i32 6, i32 0> 8; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 9; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP1]], [[TMP2]] 10; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <4 x i32> [[TMP1]], [[TMP2]] 11; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 7> 12; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]] 13; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP6]]) 14; CHECK-NEXT: ret i1 [[TMP7]] 15; 16 %x0 = extractelement <4 x i32> %x, i32 0 17 %x1 = extractelement <4 x i32> %x, i32 1 18 %x2 = extractelement <4 x i32> %x, i32 2 19 %x3 = extractelement <4 x i32> %x, i32 3 20 %c0 = icmp ult i32 %x0, 0 21 %c1 = icmp slt i32 %x1, 0 22 %c2 = icmp sgt i32 %x2, 0 23 %c3 = icmp slt i32 %x3, 0 24 %s1 = select i1 %c0, i1 %c1, i1 false 25 %s2 = select i1 %s1, i1 %c2, i1 false 26 %s3 = select i1 %s2, i1 %c3, i1 false 27 ret i1 %s3 28} 29 30define i1 @logical_and_icmp_clamp(<4 x i32> %x) { 31; CHECK-LABEL: @logical_and_icmp_clamp( 32; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> 33; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <8 x i32> [[TMP1]], <i32 17, i32 17, i32 17, i32 17, i32 42, i32 42, i32 42, i32 42> 34; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <8 x i32> [[TMP1]], <i32 17, i32 17, i32 17, i32 17, i32 42, i32 42, i32 42, i32 42> 35; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15> 36; CHECK-NEXT: [[TMP5:%.*]] = freeze <8 x i1> [[TMP4]] 37; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> [[TMP5]]) 38; CHECK-NEXT: ret i1 [[TMP6]] 39; 40 %x0 = extractelement <4 x i32> %x, i32 0 41 %x1 = extractelement <4 x i32> %x, i32 1 42 %x2 = extractelement <4 x i32> %x, i32 2 43 %x3 = extractelement <4 x i32> %x, i32 3 44 %c0 = icmp slt i32 %x0, 42 45 %c1 = icmp slt i32 %x1, 42 46 %c2 = icmp slt i32 %x2, 42 47 %c3 = icmp slt i32 %x3, 42 48 %d0 = icmp sgt i32 %x0, 17 49 %d1 = icmp sgt i32 %x1, 17 50 %d2 = icmp sgt i32 %x2, 17 51 %d3 = icmp sgt i32 %x3, 17 52 %s1 = select i1 %c0, i1 %c1, i1 false 53 %s2 = select i1 %s1, i1 %c2, i1 false 54 %s3 = select i1 %s2, i1 %c3, i1 false 55 %s4 = select i1 %s3, i1 %d0, i1 false 56 %s5 = select i1 %s4, i1 %d1, i1 false 57 %s6 = select i1 %s5, i1 %d2, i1 false 58 %s7 = select i1 %s6, i1 %d3, i1 false 59 ret i1 %s7 60} 61