1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4 5define <2 x i32> @test(i32 %arg) { 6; CHECK-LABEL: define <2 x i32> @test( 7; CHECK-SAME: i32 [[ARG:%.*]]) { 8; CHECK-NEXT: bb: 9; CHECK-NEXT: [[OR:%.*]] = or i32 [[ARG]], 0 10; CHECK-NEXT: [[MUL:%.*]] = mul i32 0, 1 11; CHECK-NEXT: [[MUL1:%.*]] = mul i32 [[OR]], [[MUL]] 12; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 0, [[MUL1]] 13; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[OR]], i32 0 14; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[MUL]], i32 1 15; CHECK-NEXT: ret <2 x i32> [[TMP1]] 16; 17bb: 18 %or = or i32 %arg, 0 19 %mul = mul i32 0, 1 20 %mul1 = mul i32 %or, %mul 21 %cmp = icmp ugt i32 0, %mul1 22 %0 = insertelement <2 x i32> poison, i32 %or, i32 0 23 %1 = insertelement <2 x i32> %0, i32 %mul, i32 1 24 ret <2 x i32> %1 25} 26 27