xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/X86/sign-extend.ll (revision 3be72f402925b99adbec4a2ee5bacdf76ba6c8d1)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
3
4define <4 x i32> @sign_extend_v_v(<4 x i16> %lhs) {
5; CHECK-LABEL: @sign_extend_v_v(
6; CHECK-NEXT:  entry:
7; CHECK-NEXT:    [[TMP0:%.*]] = sext <4 x i16> [[LHS:%.*]] to <4 x i32>
8; CHECK-NEXT:    ret <4 x i32> [[TMP0]]
9;
10entry:
11  %vecext = extractelement <4 x i16> %lhs, i32 0
12  %conv = sext i16 %vecext to i32
13  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
14  %vecext1 = extractelement <4 x i16> %lhs, i32 1
15  %conv2 = sext i16 %vecext1 to i32
16  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
17  %vecext4 = extractelement <4 x i16> %lhs, i32 2
18  %conv5 = sext i16 %vecext4 to i32
19  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
20  %vecext7 = extractelement <4 x i16> %lhs, i32 3
21  %conv8 = sext i16 %vecext7 to i32
22  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
23  ret <4 x i32> %vecinit9
24}
25
26define <4 x i16> @truncate_v_v(<4 x i32> %lhs) {
27; CHECK-LABEL: @truncate_v_v(
28; CHECK-NEXT:  entry:
29; CHECK-NEXT:    [[TMP0:%.*]] = trunc <4 x i32> [[LHS:%.*]] to <4 x i16>
30; CHECK-NEXT:    ret <4 x i16> [[TMP0]]
31;
32entry:
33  %vecext = extractelement <4 x i32> %lhs, i32 0
34  %conv = trunc i32 %vecext to i16
35  %vecinit = insertelement <4 x i16> undef, i16 %conv, i32 0
36  %vecext1 = extractelement <4 x i32> %lhs, i32 1
37  %conv2 = trunc i32 %vecext1 to i16
38  %vecinit3 = insertelement <4 x i16> %vecinit, i16 %conv2, i32 1
39  %vecext4 = extractelement <4 x i32> %lhs, i32 2
40  %conv5 = trunc i32 %vecext4 to i16
41  %vecinit6 = insertelement <4 x i16> %vecinit3, i16 %conv5, i32 2
42  %vecext7 = extractelement <4 x i32> %lhs, i32 3
43  %conv8 = trunc i32 %vecext7 to i16
44  %vecinit9 = insertelement <4 x i16> %vecinit6, i16 %conv8, i32 3
45  ret <4 x i16> %vecinit9
46}
47