xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll (revision 9bf6365237f3a8a401afc0a69d2fb6d1b809ce68) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
5
6define void @hoge(i1 %arg) {
7; CHECK-LABEL: @hoge(
8; CHECK-NEXT:  bb:
9; CHECK-NEXT:    br i1 %arg, label [[BB1:%.*]], label [[BB2:%.*]]
10; CHECK:       bb1:
11; CHECK-NEXT:    ret void
12; CHECK:       bb2:
13; CHECK-NEXT:    [[T:%.*]] = select i1 undef, i16 undef, i16 15
14; CHECK-NEXT:    [[T3:%.*]] = sext i16 undef to i32
15; CHECK-NEXT:    [[T4:%.*]] = sext i16 [[T]] to i32
16; CHECK-NEXT:    [[T5:%.*]] = sub nsw i32 undef, [[T4]]
17; CHECK-NEXT:    [[T6:%.*]] = sub i32 [[T5]], undef
18; CHECK-NEXT:    [[T7:%.*]] = sub nsw i32 63, [[T3]]
19; CHECK-NEXT:    [[T8:%.*]] = sub i32 [[T7]], undef
20; CHECK-NEXT:    [[T9:%.*]] = add i32 [[T8]], undef
21; CHECK-NEXT:    [[T10:%.*]] = add nsw i32 [[T6]], 15
22; CHECK-NEXT:    [[T11:%.*]] = icmp sgt i32 [[T9]], [[T10]]
23; CHECK-NEXT:    [[T12:%.*]] = select i1 [[T11]], i32 [[T9]], i32 [[T10]]
24; CHECK-NEXT:    [[T13:%.*]] = add nsw i32 [[T6]], 31
25; CHECK-NEXT:    [[T14:%.*]] = icmp sgt i32 [[T12]], [[T13]]
26; CHECK-NEXT:    [[T15:%.*]] = select i1 [[T14]], i32 [[T12]], i32 [[T13]]
27; CHECK-NEXT:    [[T16:%.*]] = add nsw i32 [[T6]], 47
28; CHECK-NEXT:    [[T17:%.*]] = icmp sgt i32 [[T15]], [[T16]]
29; CHECK-NEXT:    [[T18:%.*]] = select i1 [[T17]], i32 [[T15]], i32 [[T16]]
30; CHECK-NEXT:    [[T19:%.*]] = select i1 undef, i32 [[T18]], i32 undef
31; CHECK-NEXT:    [[T20:%.*]] = icmp sgt i32 [[T19]], 63
32; CHECK-NEXT:    [[T21:%.*]] = sub nsw i32 undef, [[T3]]
33; CHECK-NEXT:    [[T22:%.*]] = sub i32 [[T21]], undef
34; CHECK-NEXT:    [[T23:%.*]] = sub nsw i32 undef, [[T4]]
35; CHECK-NEXT:    [[T24:%.*]] = sub i32 [[T23]], undef
36; CHECK-NEXT:    [[T25:%.*]] = add nsw i32 [[T24]], -49
37; CHECK-NEXT:    [[OP_RDX:%.*]] = icmp sgt i32 [[T25]], undef
38; CHECK-NEXT:    [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 undef, i32 [[T25]]
39; CHECK-NEXT:    [[T28:%.*]] = icmp sgt i32 [[OP_RDX1]], undef
40; CHECK-NEXT:    [[T30:%.*]] = select i1 [[T28]], i32 undef, i32 [[OP_RDX1]]
41; CHECK-NEXT:    [[T32:%.*]] = add nsw i32 [[T22]], -33
42; CHECK-NEXT:    [[T31:%.*]] = icmp sgt i32 [[T32]], undef
43; CHECK-NEXT:    [[T35:%.*]] = select i1 [[T31]], i32 undef, i32 [[T32]]
44; CHECK-NEXT:    [[OP_RDX2:%.*]] = icmp sgt i32 [[T35]], [[T30]]
45; CHECK-NEXT:    [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[T30]], i32 [[T35]]
46; CHECK-NEXT:    [[T39:%.*]] = add nsw i32 [[T24]], -33
47; CHECK-NEXT:    [[T36:%.*]] = icmp sgt i32 [[T39]], undef
48; CHECK-NEXT:    [[T37:%.*]] = select i1 [[T36]], i32 undef, i32 [[T39]]
49; CHECK-NEXT:    [[T38:%.*]] = icmp sgt i32 [[T37]], [[OP_RDX3]]
50; CHECK-NEXT:    [[OP_RDX5:%.*]] = select i1 [[T38]], i32 [[OP_RDX3]], i32 [[T37]]
51; CHECK-NEXT:    [[T42:%.*]] = add nsw i32 [[T22]], -17
52; CHECK-NEXT:    [[T41:%.*]] = icmp sgt i32 [[T42]], undef
53; CHECK-NEXT:    [[T40:%.*]] = select i1 [[T41]], i32 undef, i32 [[T42]]
54; CHECK-NEXT:    [[OP_RDX6:%.*]] = icmp sgt i32 [[T40]], [[OP_RDX5]]
55; CHECK-NEXT:    [[OP_RDX7:%.*]] = select i1 [[OP_RDX6]], i32 [[OP_RDX5]], i32 [[T40]]
56; CHECK-NEXT:    [[T45:%.*]] = icmp sgt i32 undef, [[OP_RDX7]]
57; CHECK-NEXT:    unreachable
58;
59bb:
60  br i1 %arg, label %bb1, label %bb2
61
62bb1:                                              ; preds = %bb
63  ret void
64
65bb2:                                              ; preds = %bb
66  %t = select i1 undef, i16 undef, i16 15
67  %t3 = sext i16 undef to i32
68  %t4 = sext i16 %t to i32
69  %t5 = sub nsw i32 undef, %t4
70  %t6 = sub i32 %t5, undef
71  %t7 = sub nsw i32 63, %t3
72  %t8 = sub i32 %t7, undef
73  %t9 = add i32 %t8, undef
74  %t10 = add nsw i32 %t6, 15
75  %t11 = icmp sgt i32 %t9, %t10
76  %t12 = select i1 %t11, i32 %t9, i32 %t10
77  %t13 = add nsw i32 %t6, 31
78  %t14 = icmp sgt i32 %t12, %t13
79  %t15 = select i1 %t14, i32 %t12, i32 %t13
80  %t16 = add nsw i32 %t6, 47
81  %t17 = icmp sgt i32 %t15, %t16
82  %t18 = select i1 %t17, i32 %t15, i32 %t16
83  %t19 = select i1 undef, i32 %t18, i32 undef
84  %t20 = icmp sgt i32 %t19, 63
85  %t21 = sub nsw i32 undef, %t3
86  %t22 = sub i32 %t21, undef
87  %t23 = sub nsw i32 undef, %t4
88  %t24 = sub i32 %t23, undef
89  %t25 = add nsw i32 %t24, -49
90  %t26 = icmp sgt i32 %t25, undef
91  %t27 = select i1 %t26, i32 undef, i32 %t25
92  %t28 = icmp sgt i32 %t27, undef
93  %t29 = select i1 %t28, i32 undef, i32 %t27
94  %t30 = add nsw i32 %t22, -33
95  %t31 = icmp sgt i32 %t30, undef
96  %t32 = select i1 %t31, i32 undef, i32 %t30
97  %t33 = icmp sgt i32 %t32, %t29
98  %t34 = select i1 %t33, i32 %t29, i32 %t32
99  %t35 = add nsw i32 %t24, -33
100  %t36 = icmp sgt i32 %t35, undef
101  %t37 = select i1 %t36, i32 undef, i32 %t35
102  %t38 = icmp sgt i32 %t37, %t34
103  %t39 = select i1 %t38, i32 %t34, i32 %t37
104  %t40 = add nsw i32 %t22, -17
105  %t41 = icmp sgt i32 %t40, undef
106  %t42 = select i1 %t41, i32 undef, i32 %t40
107  %t43 = icmp sgt i32 %t42, %t39
108  %t44 = select i1 %t43, i32 %t39, i32 %t42
109  %t45 = icmp sgt i32 undef, %t44
110  unreachable
111}
112
113