1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake-avx512 | FileCheck %s 3 4define void @test() { 5; CHECK-LABEL: @test( 6; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr undef, i64 4 7; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 0 8; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1 9; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[TMP3]] to <4 x i16> 10; CHECK-NEXT: [[TMP5:%.*]] = sub <4 x i16> zeroinitializer, [[TMP4]] 11; CHECK-NEXT: [[TMP6:%.*]] = shl <4 x i16> [[TMP5]], zeroinitializer 12; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i16> [[TMP6]], zeroinitializer 13; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i16> [[TMP7]], <4 x i16> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 14; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i16> [[TMP7]], [[TMP8]] 15; CHECK-NEXT: [[TMP10:%.*]] = sub <4 x i16> [[TMP7]], [[TMP8]] 16; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i32> <i32 1, i32 4, i32 3, i32 6> 17; CHECK-NEXT: [[TMP12:%.*]] = add <4 x i16> zeroinitializer, [[TMP11]] 18; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i16> zeroinitializer, [[TMP11]] 19; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i32> <i32 0, i32 1, i32 6, i32 7> 20; CHECK-NEXT: [[TMP15:%.*]] = sext <4 x i16> [[TMP14]] to <4 x i32> 21; CHECK-NEXT: store <4 x i32> [[TMP15]], ptr [[TMP2]], align 16 22; CHECK-NEXT: ret void 23; 24 %1 = getelementptr inbounds i8, ptr undef, i64 4 25 %2 = load i8, ptr %1, align 1 26 %3 = zext i8 %2 to i32 27 %4 = sub nsw i32 0, %3 28 %5 = shl nsw i32 %4, 0 29 %6 = add nsw i32 %5, 0 30 %7 = getelementptr inbounds i8, ptr undef, i64 5 31 %8 = load i8, ptr %7, align 1 32 %9 = zext i8 %8 to i32 33 %10 = sub nsw i32 0, %9 34 %11 = shl nsw i32 %10, 0 35 %12 = add nsw i32 %11, 0 36 %13 = getelementptr inbounds i8, ptr undef, i64 6 37 %14 = load i8, ptr %13, align 1 38 %15 = zext i8 %14 to i32 39 %16 = sub nsw i32 0, %15 40 %17 = shl nsw i32 %16, 0 41 %18 = add nsw i32 %17, 0 42 %19 = getelementptr inbounds i8, ptr undef, i64 7 43 %20 = load i8, ptr %19, align 1 44 %21 = zext i8 %20 to i32 45 %22 = sub nsw i32 0, %21 46 %23 = shl nsw i32 %22, 0 47 %24 = add nsw i32 %23, 0 48 %25 = add nsw i32 %12, %6 49 %26 = sub nsw i32 %6, %12 50 %27 = add nsw i32 %24, %18 51 %28 = sub nsw i32 %18, %24 52 %29 = add nsw i32 0, %25 53 %30 = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 0 54 store i32 %29, ptr %30, align 16 55 %31 = sub nsw i32 0, %27 56 %32 = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 2 57 store i32 %31, ptr %32, align 8 58 %33 = add nsw i32 0, %26 59 %34 = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 1 60 store i32 %33, ptr %34, align 4 61 %35 = sub nsw i32 0, %28 62 %36 = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 3 63 store i32 %35, ptr %36, align 4 64 ret void 65} 66