1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=i686-pc-win32 -mcpu=corei7-avx | FileCheck %s 3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-unknown-linux" 6 7@e = dso_local global i32 0, align 4 8@f = dso_local local_unnamed_addr global i32 0, align 4 9@d = dso_local global i32 0, align 4 10@c = dso_local global i32 0, align 4 11@b = dso_local global i32 0, align 4 12@a = dso_local local_unnamed_addr global i32 0, align 4 13 14define dso_local i32 @main() { 15; CHECK-LABEL: @main( 16; CHECK-NEXT: entry: 17; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @e, align 4 18; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @f, align 4 19; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] 20; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 21; CHECK: if.then: 22; CHECK-NEXT: [[TMP2:%.*]] = load volatile i32, ptr @d, align 4 23; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, ptr @c, align 4 24; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP3]], 0 25; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]] 26; CHECK: lor.rhs: 27; CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @d, align 4 28; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i32 [[TMP4]], 0 29; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL1]] to i32 30; CHECK-NEXT: br label [[LOR_END]] 31; CHECK: lor.end: 32; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ 1, [[IF_THEN]] ], [ [[PHI_CAST]], [[LOR_RHS]] ] 33; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP1]], 0 34; CHECK-NEXT: [[LAND_EXT:%.*]] = zext i1 [[TOBOOL2]] to i32 35; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP5]], [[LAND_EXT]] 36; CHECK-NEXT: store volatile i32 [[OR]], ptr @b, align 4 37; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP1]], [[TMP2]] 38; CHECK-NEXT: [[TMP6:%.*]] = load volatile i32, ptr @d, align 4 39; CHECK-NEXT: [[TOBOOL4_NOT:%.*]] = icmp eq i32 [[TMP6]], 0 40; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label [[LAND_END7:%.*]], label [[LAND_RHS5:%.*]] 41; CHECK: land.rhs5: 42; CHECK-NEXT: [[TMP7:%.*]] = load volatile i32, ptr @c, align 4 43; CHECK-NEXT: [[TOBOOL6:%.*]] = icmp ne i32 [[TMP7]], 0 44; CHECK-NEXT: [[PHI_CAST11:%.*]] = zext i1 [[TOBOOL6]] to i32 45; CHECK-NEXT: br label [[LAND_END7]] 46; CHECK: land.end7: 47; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ 0, [[LOR_END]] ], [ [[PHI_CAST11]], [[LAND_RHS5]] ] 48; CHECK-NEXT: [[OR9:%.*]] = or i32 [[TMP8]], [[DIV]] 49; CHECK-NEXT: store i32 [[OR9]], ptr @a, align 4 50; CHECK-NEXT: br label [[IF_END]] 51; CHECK: if.end: 52; CHECK-NEXT: ret i32 0 53; 54entry: 55 %0 = load volatile i32, ptr @e, align 4 56 %1 = load i32, ptr @f, align 4 57 %cmp = icmp sgt i32 %0, %1 58 br i1 %cmp, label %if.then, label %if.end 59 60if.then: ; preds = %entry 61 %2 = load volatile i32, ptr @d, align 4 62 %3 = load volatile i32, ptr @c, align 4 63 %tobool.not = icmp eq i32 %3, 0 64 br i1 %tobool.not, label %lor.rhs, label %lor.end 65 66lor.rhs: ; preds = %if.then 67 %4 = load volatile i32, ptr @d, align 4 68 %tobool1 = icmp ne i32 %4, 0 69 %phi.cast = zext i1 %tobool1 to i32 70 br label %lor.end 71 72lor.end: ; preds = %lor.rhs, %if.then 73 %5 = phi i32 [ 1, %if.then ], [ %phi.cast, %lor.rhs ] 74 %tobool2 = icmp ne i32 %1, 0 75 %land.ext = zext i1 %tobool2 to i32 76 %or = or i32 %5, %land.ext 77 store volatile i32 %or, ptr @b, align 4 78 %div = sdiv i32 %1, %2 79 %6 = load volatile i32, ptr @d, align 4 80 %tobool4.not = icmp eq i32 %6, 0 81 br i1 %tobool4.not, label %land.end7, label %land.rhs5 82 83land.rhs5: ; preds = %lor.end 84 %7 = load volatile i32, ptr @c, align 4 85 %tobool6 = icmp ne i32 %7, 0 86 %phi.cast11 = zext i1 %tobool6 to i32 87 br label %land.end7 88 89land.end7: ; preds = %land.rhs5, %lor.end 90 %8 = phi i32 [ 0, %lor.end ], [ %phi.cast11, %land.rhs5 ] 91 %or9 = or i32 %8, %div 92 store i32 %or9, ptr @a, align 4 93 br label %if.end 94 95if.end: ; preds = %land.end7, %entry 96 ret i32 0 97} 98