1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s 3; These code should be fully vectorized by D57059 patch 4 5target triple = "x86_64-unknown-linux-gnu" 6 7define <4 x i32> @foo(<4 x i32> %x, i32 %f) { 8; CHECK-LABEL: @foo( 9; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i64 0 10; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[F]], 1 11; CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[ADD]], i64 1 12; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[F]], i64 0 13; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer 14; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 2, i32 3> 15; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> 16; CHECK-NEXT: [[VECINIT51:%.*]] = shufflevector <4 x i32> [[VECINIT1]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> 17; CHECK-NEXT: ret <4 x i32> [[VECINIT51]] 18; 19 %vecinit = insertelement <4 x i32> undef, i32 %f, i32 0 20 %add = add nsw i32 %f, 1 21 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %add, i32 1 22 %add2 = add nsw i32 %f, 2 23 %vecinit3 = insertelement <4 x i32> %vecinit1, i32 %add2, i32 2 24 %add4 = add nsw i32 %f, 3 25 %vecinit5 = insertelement <4 x i32> %vecinit3, i32 %add4, i32 3 26 ret <4 x i32> %vecinit5 27} 28 29define <4 x i32> @bar(<4 x i32> %x, i32 %f) { 30; CHECK-LABEL: @bar( 31; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[F:%.*]], i64 0 32; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer 33; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 2, i32 3> 34; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1> 35; CHECK-NEXT: ret <4 x i32> [[TMP4]] 36; 37 %add = add nsw i32 %f, 2 38 %vecinit = insertelement <4 x i32> undef, i32 %add, i32 0 39 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %add, i32 1 40 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %add, i32 2 41 %add5 = add nsw i32 %f, 3 42 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %add5, i32 3 43 ret <4 x i32> %vecinit6 44} 45