xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll (revision 9abb1ffc5cb75465340cb604988d1e386415bd72)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2; RUN: opt -S -passes=slp-vectorizer -slp-threshold=-9999 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
3; RUN: opt -S -passes=slp-vectorizer -slp-threshold=-9999 -mtriple=x86_64-unknown-linux-gnu\
4; RUN: -slp-skip-early-profitability-check < %s | FileCheck %s --check-prefixes=FORCED
5
6define void @foo() {
7; FORCED-LABEL: define void @foo() {
8; FORCED-NEXT:  bb:
9; FORCED-NEXT:    [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 0, i32 0
10; FORCED-NEXT:    br label [[BB1:%.*]]
11; FORCED:       bb1:
12; FORCED-NEXT:    [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, [[BB:%.*]] ], [ [[TMP6:%.*]], [[BB4:%.*]] ]
13; FORCED-NEXT:    [[TMP2:%.*]] = shl <2 x i32> [[TMP1]], [[TMP0]]
14; FORCED-NEXT:    [[TMP3:%.*]] = or <2 x i32> [[TMP1]], [[TMP0]]
15; FORCED-NEXT:    [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 0, i32 3>
16; FORCED-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> [[TMP1]], <2 x i32> <i32 0, i32 3>
17; FORCED-NEXT:    [[TMP6]] = or <2 x i32> [[TMP5]], zeroinitializer
18; FORCED-NEXT:    [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0
19; FORCED-NEXT:    [[CALL:%.*]] = call i64 null(i32 [[TMP7]])
20; FORCED-NEXT:    br label [[BB4]]
21; FORCED:       bb4:
22; FORCED-NEXT:    br i1 false, label [[BB5:%.*]], label [[BB1]]
23; FORCED:       bb5:
24; FORCED-NEXT:    [[TMP8:%.*]] = phi <2 x i32> [ [[TMP4]], [[BB4]] ]
25; FORCED-NEXT:    ret void
26;
27; CHECK-LABEL: define void @foo() {
28; CHECK-NEXT:  bb:
29; CHECK-NEXT:    br label [[BB1:%.*]]
30; CHECK:       bb1:
31; CHECK-NEXT:    [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, [[BB:%.*]] ], [ [[TMP6:%.*]], [[BB4:%.*]] ]
32; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
33; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[TMP2]], 0
34; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[SHL]], i32 0
35; CHECK-NEXT:    [[TMP6]] = or <2 x i32> [[TMP5]], zeroinitializer
36; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0
37; CHECK-NEXT:    [[CALL:%.*]] = call i64 null(i32 [[TMP7]])
38; CHECK-NEXT:    br label [[BB4]]
39; CHECK:       bb4:
40; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i32> [[TMP6]], i32 1
41; CHECK-NEXT:    br i1 false, label [[BB5:%.*]], label [[BB1]]
42; CHECK:       bb5:
43; CHECK-NEXT:    [[PHI6:%.*]] = phi i32 [ [[SHL]], [[BB4]] ]
44; CHECK-NEXT:    [[PHI7:%.*]] = phi i32 [ [[TMP8]], [[BB4]] ]
45; CHECK-NEXT:    ret void
46;
47bb:
48  br label %bb1
49
50bb1:
51  %phi = phi i32 [ 0, %bb ], [ %or, %bb4 ]
52  %phi2 = phi i32 [ 0, %bb ], [ %or3, %bb4 ]
53  %and = and i32 0, 0
54  %shl = shl i32 %phi, %and
55  %or = or i32 %shl, 0
56  %call = call i64 null(i32 %or)
57  %or3 = or i32 %phi2, 0
58  br label %bb4
59
60bb4:
61  br i1 false, label %bb5, label %bb1
62
63bb5:
64  %phi6 = phi i32 [ %shl, %bb4 ]
65  %phi7 = phi i32 [ %or3, %bb4 ]
66  ret void
67}
68