1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-7 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s 3 4define void @test(i64 %d.promoted.i) { 5; CHECK-LABEL: define void @test( 6; CHECK-SAME: i64 [[D_PROMOTED_I:%.*]]) { 7; CHECK-NEXT: entry: 8; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[D_PROMOTED_I]], i32 0 9; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> zeroinitializer, [[TMP1]] 10; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i1> 11; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i1> @llvm.vector.insert.v16i1.v2i1(<16 x i1> poison, <2 x i1> [[TMP3]], i64 0) 12; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <16 x i1> [[TMP4]], <16 x i1> <i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 1, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 13; CHECK-NEXT: [[TMP6:%.*]] = mul <16 x i1> [[TMP5]], zeroinitializer 14; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP6]]) 15; CHECK-NEXT: [[TMP9:%.*]] = zext i1 [[TMP8]] to i32 16; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 0 17; CHECK-NEXT: store i32 [[TMP10]], ptr null, align 4 18; CHECK-NEXT: ret void 19; 20entry: 21 %add.1.i = add i64 0, 0 22 %and.1.i = and i64 %add.1.i, %d.promoted.i 23 %conv12.1.i = trunc i64 %and.1.i to i32 24 %mul.i.1.i = mul i32 %conv12.1.i, 0 25 %conv12.i = trunc i64 0 to i32 26 %mul.i.i = mul i32 %conv12.i, 0 27 %conv14104.i = or i32 %mul.i.1.i, %mul.i.i 28 %conv12.2.i = trunc i64 0 to i32 29 %mul.i.2.i = mul i32 %conv12.2.i, 0 30 %0 = or i32 %conv14104.i, %mul.i.2.i 31 %conv12.182.i = trunc i64 0 to i32 32 %mul.i.183.i = mul i32 %conv12.182.i, 0 33 %1 = or i32 %0, %mul.i.183.i 34 %conv12.1.1.i = trunc i64 0 to i32 35 %mul.i.1.1.i = mul i32 %conv12.1.1.i, 0 36 %2 = or i32 %1, %mul.i.1.1.i 37 %conv12.2.1.i = trunc i64 0 to i32 38 %mul.i.2.1.i = mul i32 %conv12.2.1.i, 0 39 %3 = or i32 %2, %mul.i.2.1.i 40 %conv12.297.i = trunc i64 0 to i32 41 %mul.i.298.i = mul i32 %conv12.297.i, 0 42 %4 = or i32 %3, %mul.i.298.i 43 %conv12.1.2.i = trunc i64 0 to i32 44 %mul.i.1.2.i = mul i32 %conv12.1.2.i, 0 45 %5 = or i32 %4, %mul.i.1.2.i 46 %add.1.i.1 = add i64 0, 0 47 %and.1.i.1 = and i64 %add.1.i.1, 0 48 %conv12.1.i.1 = trunc i64 %and.1.i.1 to i32 49 %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 0 50 %conv12.i.1 = trunc i64 0 to i32 51 %mul.i.i.1 = mul i32 %conv12.i.1, 0 52 %conv14104.i.1 = or i32 %mul.i.1.i.1, %mul.i.i.1 53 %conv12.2.i.1 = trunc i64 0 to i32 54 %mul.i.2.i.1 = mul i32 %conv12.2.i.1, 0 55 %6 = or i32 %conv14104.i.1, %mul.i.2.i.1 56 %conv12.182.i.1 = trunc i64 0 to i32 57 %mul.i.183.i.1 = mul i32 %conv12.182.i.1, 0 58 %7 = or i32 %6, %mul.i.183.i.1 59 %conv12.1.1.i.1 = trunc i64 0 to i32 60 %mul.i.1.1.i.1 = mul i32 %conv12.1.1.i.1, 0 61 %8 = or i32 %7, %mul.i.1.1.i.1 62 %conv12.2.1.i.1 = trunc i64 0 to i32 63 %mul.i.2.1.i.1 = mul i32 %conv12.2.1.i.1, 0 64 %9 = or i32 %8, %mul.i.2.1.i.1 65 %conv12.297.i.1 = trunc i64 0 to i32 66 %mul.i.298.i.1 = mul i32 %conv12.297.i.1, 0 67 %10 = or i32 %9, %mul.i.298.i.1 68 %conv12.1.2.i.1 = trunc i64 0 to i32 69 %mul.i.1.2.i.1 = mul i32 %conv12.1.2.i.1, 0 70 %11 = or i32 %10, %mul.i.1.2.i.1 71 %12 = or i32 %5, %11 72 %13 = and i32 %12, 0 73 store i32 %13, ptr null, align 4 74 ret void 75} 76