1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=slp-vectorizer -mcpu=skx -S -o - -mtriple=x86_64-unknown < %s | FileCheck %s 3 4define void @test(ptr %0, double %1) { 5; CHECK-LABEL: @test( 6; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[TMP0:%.*]], i32 6 7; CHECK-NEXT: br label [[TMP4:%.*]] 8; CHECK: 4: 9; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP1:%.*]], i32 1 10; CHECK-NEXT: br label [[TMP6:%.*]] 11; CHECK: 6: 12; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr null, align 8 13; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP7]], i32 1 14; CHECK-NEXT: [[TMP9:%.*]] = fcmp olt <2 x double> [[TMP5]], [[TMP8]] 15; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP9]], <2 x double> zeroinitializer, <2 x double> zeroinitializer 16; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP10]], zeroinitializer 17; CHECK-NEXT: [[TMP12:%.*]] = fadd <2 x double> zeroinitializer, [[TMP11]] 18; CHECK-NEXT: store <2 x double> [[TMP12]], ptr [[TMP3]], align 8 19; CHECK-NEXT: br label [[TMP6]] 20; 21 %3 = getelementptr inbounds double, ptr %0, i32 6 22 %4 = getelementptr inbounds double, ptr %0, i32 7 23 br label %5 24 255: ; preds = %2 26 br label %6 27 286: ; preds = %6, %5 29 %7 = load double, ptr null, align 8 30 %8 = fcmp olt double 0.000000e+00, 0.000000e+00 31 %9 = select i1 %8, double 0.000000e+00, double 0.000000e+00 32 %10 = fcmp ogt double %7, %1 33 %11 = select i1 %10, double 0.000000e+00, double 0.000000e+00 34 %12 = fmul double %9, 0.000000e+00 35 %13 = fmul double 0.000000e+00, %11 36 %14 = fadd double 0.000000e+00, %12 37 store double %14, ptr %3, align 8 38 %15 = fadd double 0.000000e+00, %13 39 store double %15, ptr %4, align 8 40 br label %6 41} 42 43define { <2 x float>, <2 x float> } @test1(i32 %conv.i32.i.i.i) { 44; CHECK-LABEL: @test1( 45; CHECK-NEXT: entry: 46; CHECK-NEXT: [[CONV_I32_I_I_I1:%.*]] = fptosi float 0.000000e+00 to i32 47; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, i32 [[CONV_I32_I_I_I:%.*]], i32 0 48; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CONV_I32_I_I_I1]], i32 2 49; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[TMP1]], zeroinitializer 50; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP1]], zeroinitializer 51; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 6, i32 3> 52; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP4]], <4 x float> zeroinitializer, <4 x float> zeroinitializer 53; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[TMP5]], zeroinitializer 54; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> poison, <2 x i32> <i32 0, i32 1> 55; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> poison, <2 x i32> <i32 2, i32 3> 56; CHECK-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } zeroinitializer, <2 x float> [[TMP7]], 0 57; CHECK-NEXT: [[DOTFCA_1_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } [[DOTFCA_0_INSERT]], <2 x float> [[TMP8]], 1 58; CHECK-NEXT: ret { <2 x float>, <2 x float> } zeroinitializer 59; 60entry: 61 %cmp.i.i.i.i.i = icmp slt i32 0, 0 62 %cond.i.i.i.i = select i1 %cmp.i.i.i.i.i, float 0.000000e+00, float 0.000000e+00 63 %conv.i32.i.i.i1 = fptosi float 0.000000e+00 to i32 64 %cmp.i.i34.i.i.i = icmp slt i32 %conv.i32.i.i.i1, 0 65 %cond.i35.i.i.i = select i1 %cmp.i.i34.i.i.i, float 0.000000e+00, float 0.000000e+00 66 %cmp.i.i38.i.i.i = icmp sgt i32 0, 0 67 %cond.i39.i.i.i = select i1 %cmp.i.i38.i.i.i, float 0.000000e+00, float 0.000000e+00 68 %cmp.i.i42.i.i.i = icmp sgt i32 %conv.i32.i.i.i, 0 69 %cond.i43.i.i.i = select i1 %cmp.i.i42.i.i.i, float 0.000000e+00, float 0.000000e+00 70 %add.i.i = fadd float 0.000000e+00, 0.000000e+00 71 %add4.i.i = fadd float 0.000000e+00, 0.000000e+00 72 %add.i9.i = fadd float %cond.i43.i.i.i, %add.i.i 73 %retval.sroa.0.0.vec.insert4 = insertelement <2 x float> zeroinitializer, float %add.i9.i, i64 0 74 %add4.i12.i = fadd float %cond.i39.i.i.i, %add4.i.i 75 %retval.sroa.0.4.vec.insert7 = insertelement <2 x float> %retval.sroa.0.0.vec.insert4, float %add4.i12.i, i64 1 76 %add.i15.i = fadd float %cond.i35.i.i.i, %add.i.i 77 %retval.sroa.7.8.vec.insert11 = insertelement <2 x float> zeroinitializer, float %add.i15.i, i64 0 78 %add4.i18.i = fadd float %cond.i.i.i.i, %add4.i.i 79 %retval.sroa.7.12.vec.insert13 = insertelement <2 x float> %retval.sroa.7.8.vec.insert11, float %add4.i18.i, i64 1 80 %.fca.0.insert = insertvalue { <2 x float>, <2 x float> } zeroinitializer, <2 x float> %retval.sroa.0.4.vec.insert7, 0 81 %.fca.1.insert = insertvalue { <2 x float>, <2 x float> } %.fca.0.insert, <2 x float> %retval.sroa.7.12.vec.insert13, 1 82 ret { <2 x float>, <2 x float> } zeroinitializer 83} 84