154ca1e2cSAlexey Bataev; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 254ca1e2cSAlexey Bataev; RUN: opt -S --passes=slp-vectorizer -mtriple=systemz -mcpu=z15 %s | FileCheck %s 354ca1e2cSAlexey Bataev 454ca1e2cSAlexey Bataevdefine void @test(ptr %a, i8 %0, i16 %b.promoted.i) { 554ca1e2cSAlexey Bataev; CHECK-LABEL: define void @test( 654ca1e2cSAlexey Bataev; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] { 754ca1e2cSAlexey Bataev; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 854ca1e2cSAlexey Bataev; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer 9*58a94b1dSAlexey Bataev; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16 1037ae4ad0SAlexey Bataev; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 1137ae4ad0SAlexey Bataev; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer 1254ca1e2cSAlexey Bataev; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] 13d94dc5f0SAlexey Bataev; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]]) 14d94dc5f0SAlexey Bataev; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP9]] to i64 1554ca1e2cSAlexey Bataev; CHECK-NEXT: [[OP_RDX:%.*]] = and i64 [[TMP11]], 1 1654ca1e2cSAlexey Bataev; CHECK-NEXT: store i64 [[OP_RDX]], ptr [[A]], align 8 1754ca1e2cSAlexey Bataev; CHECK-NEXT: ret void 1854ca1e2cSAlexey Bataev; 1954ca1e2cSAlexey Bataev %2 = zext i8 %0 to i128 2054ca1e2cSAlexey Bataev %3 = zext i16 %b.promoted.i to i128 2154ca1e2cSAlexey Bataev %4 = or i128 %3, %2 2254ca1e2cSAlexey Bataev %5 = trunc i128 %4 to i64 2354ca1e2cSAlexey Bataev %6 = and i64 %5, 1 2454ca1e2cSAlexey Bataev %7 = zext i16 %b.promoted.i to i128 2554ca1e2cSAlexey Bataev %8 = or i128 %7, %2 2654ca1e2cSAlexey Bataev %9 = trunc i128 %8 to i64 2754ca1e2cSAlexey Bataev %10 = and i64 %6, %9 2854ca1e2cSAlexey Bataev %11 = zext i16 %b.promoted.i to i128 2954ca1e2cSAlexey Bataev %12 = or i128 %11, %2 3054ca1e2cSAlexey Bataev %13 = trunc i128 %12 to i64 3154ca1e2cSAlexey Bataev %14 = and i64 %10, %13 3254ca1e2cSAlexey Bataev %15 = zext i16 %b.promoted.i to i128 3354ca1e2cSAlexey Bataev %16 = or i128 %15, %2 3454ca1e2cSAlexey Bataev %17 = trunc i128 %16 to i64 3554ca1e2cSAlexey Bataev %18 = and i64 %14, %17 3654ca1e2cSAlexey Bataev store i64 %18, ptr %a, align 8 3754ca1e2cSAlexey Bataev ret void 3854ca1e2cSAlexey Bataev} 3954ca1e2cSAlexey Bataev 40