1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -S --passes=slp-vectorizer -mtriple=systemz -mcpu=z15 %s | FileCheck %s 3 4define void @test(ptr %a, i8 %0, i16 %b.promoted.i) { 5; CHECK-LABEL: define void @test( 6; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] { 7; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 8; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer 9; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16 10; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 11; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer 12; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] 13; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]]) 14; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP9]] to i64 15; CHECK-NEXT: [[OP_RDX:%.*]] = and i64 [[TMP11]], 1 16; CHECK-NEXT: store i64 [[OP_RDX]], ptr [[A]], align 8 17; CHECK-NEXT: ret void 18; 19 %2 = zext i8 %0 to i128 20 %3 = zext i16 %b.promoted.i to i128 21 %4 = or i128 %3, %2 22 %5 = trunc i128 %4 to i64 23 %6 = and i64 %5, 1 24 %7 = zext i16 %b.promoted.i to i128 25 %8 = or i128 %7, %2 26 %9 = trunc i128 %8 to i64 27 %10 = and i64 %6, %9 28 %11 = zext i16 %b.promoted.i to i128 29 %12 = or i128 %11, %2 30 %13 = trunc i128 %12 to i64 31 %14 = and i64 %10, %13 32 %15 = zext i16 %b.promoted.i to i128 33 %16 = or i128 %15, %2 34 %17 = trunc i128 %16 to i64 35 %18 = and i64 %14, %17 36 store i64 %18, ptr %a, align 8 37 ret void 38} 39 40