xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/RISCV/smax-unsigned-operand.ll (revision 26ebe16d78b22329d602db0398ce163ad610b0dc)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s
3target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
4target triple = "riscv64-unknown-linux-gnu"
5
6@e = global [2 x i8] zeroinitializer
7
8define void @main(ptr noalias %p) {
9; CHECK-LABEL: define void @main(
10; CHECK-SAME: ptr noalias [[P:%.*]]) #[[ATTR0:[0-9]+]] {
11; CHECK-NEXT:  bb:
12; CHECK-NEXT:    [[CONV_4:%.*]] = zext i32 0 to i64
13; CHECK-NEXT:    [[COND_4:%.*]] = tail call i64 @llvm.smax.i64(i64 [[CONV_4]], i64 0)
14; CHECK-NEXT:    [[CONV5_4:%.*]] = trunc i64 [[COND_4]] to i8
15; CHECK-NEXT:    store i8 [[CONV5_4]], ptr getelementptr inbounds ([11 x i8], ptr @e, i64 0, i64 4), align 1
16; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[P]], align 4
17; CHECK-NEXT:    [[CONV_5:%.*]] = zext i32 [[TMP0]] to i64
18; CHECK-NEXT:    [[COND_5:%.*]] = tail call i64 @llvm.smax.i64(i64 [[CONV_5]], i64 1)
19; CHECK-NEXT:    [[CONV5_5:%.*]] = trunc i64 [[COND_5]] to i8
20; CHECK-NEXT:    store i8 [[CONV5_5]], ptr getelementptr inbounds ([11 x i8], ptr @e, i64 0, i64 5), align 1
21; CHECK-NEXT:    ret void
22;
23bb:
24  %conv.4 = zext i32 0 to i64
25  %cond.4 = tail call i64 @llvm.smax.i64(i64 %conv.4, i64 0)
26  %conv5.4 = trunc i64 %cond.4 to i8
27  store i8 %conv5.4, ptr getelementptr inbounds ([11 x i8], ptr @e, i64 0, i64 4), align 1
28  %0 = load i32, ptr %p, align 4
29  %conv.5 = zext i32 %0 to i64
30  %cond.5 = tail call i64 @llvm.smax.i64(i64 %conv.5, i64 1)
31  %conv5.5 = trunc i64 %cond.5 to i8
32  store i8 %conv5.5, ptr getelementptr inbounds ([11 x i8], ptr @e, i64 0, i64 5), align 1
33  ret void
34}
35
36