1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s 3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s 5 6define <2 x i16> @bswap_v2i16(<2 x i16> %arg) { 7; GFX7-LABEL: @bswap_v2i16( 8; GFX7-NEXT: bb: 9; GFX7-NEXT: [[T:%.*]] = extractelement <2 x i16> [[ARG:%.*]], i64 0 10; GFX7-NEXT: [[T1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[T]]) 11; GFX7-NEXT: [[T2:%.*]] = insertelement <2 x i16> undef, i16 [[T1]], i64 0 12; GFX7-NEXT: [[T3:%.*]] = extractelement <2 x i16> [[ARG]], i64 1 13; GFX7-NEXT: [[T4:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[T3]]) 14; GFX7-NEXT: [[T5:%.*]] = insertelement <2 x i16> [[T2]], i16 [[T4]], i64 1 15; GFX7-NEXT: ret <2 x i16> [[T5]] 16; 17; GFX8-LABEL: @bswap_v2i16( 18; GFX8-NEXT: bb: 19; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[ARG:%.*]]) 20; GFX8-NEXT: ret <2 x i16> [[TMP0]] 21; 22bb: 23 %t = extractelement <2 x i16> %arg, i64 0 24 %t1 = tail call i16 @llvm.bswap.i16(i16 %t) 25 %t2 = insertelement <2 x i16> undef, i16 %t1, i64 0 26 %t3 = extractelement <2 x i16> %arg, i64 1 27 %t4 = tail call i16 @llvm.bswap.i16(i16 %t3) 28 %t5 = insertelement <2 x i16> %t2, i16 %t4, i64 1 29 ret <2 x i16> %t5 30} 31 32define <2 x i32> @bswap_v2i32(<2 x i32> %arg) { 33; GCN-LABEL: @bswap_v2i32( 34; GCN-NEXT: bb: 35; GCN-NEXT: [[T:%.*]] = extractelement <2 x i32> [[ARG:%.*]], i64 0 36; GCN-NEXT: [[T1:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T]]) 37; GCN-NEXT: [[T2:%.*]] = insertelement <2 x i32> undef, i32 [[T1]], i64 0 38; GCN-NEXT: [[T3:%.*]] = extractelement <2 x i32> [[ARG]], i64 1 39; GCN-NEXT: [[T4:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T3]]) 40; GCN-NEXT: [[T5:%.*]] = insertelement <2 x i32> [[T2]], i32 [[T4]], i64 1 41; GCN-NEXT: ret <2 x i32> [[T5]] 42; 43bb: 44 %t = extractelement <2 x i32> %arg, i64 0 45 %t1 = tail call i32 @llvm.bswap.i32(i32 %t) 46 %t2 = insertelement <2 x i32> undef, i32 %t1, i64 0 47 %t3 = extractelement <2 x i32> %arg, i64 1 48 %t4 = tail call i32 @llvm.bswap.i32(i32 %t3) 49 %t5 = insertelement <2 x i32> %t2, i32 %t4, i64 1 50 ret <2 x i32> %t5 51} 52 53declare i16 @llvm.bswap.i16(i16) #0 54declare i32 @llvm.bswap.i32(i32) #0 55 56attributes #0 = { nounwind readnone speculatable willreturn } 57