xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll (revision 9bf6365237f3a8a401afc0a69d2fb6d1b809ce68)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s
3target triple = "aarch64-unknown-linux-gnu"
4@d = internal unnamed_addr global i32 5, align 4
5
6define dso_local void @l(i1 %arg) local_unnamed_addr {
7; CHECK-LABEL: @l(
8; CHECK-NEXT:  bb:
9; CHECK-NEXT:    br label [[BB1:%.*]]
10; CHECK:       bb1:
11; CHECK-NEXT:    [[TMP0:%.*]] = phi <2 x i16> [ undef, [[BB:%.*]] ], [ [[TMP9:%.*]], [[BB25:%.*]] ]
12; CHECK-NEXT:    br i1 %arg, label [[BB3:%.*]], label [[BB11:%.*]]
13; CHECK:       bb3:
14; CHECK-NEXT:    [[I4:%.*]] = zext i1 undef to i32
15; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i16> [[TMP0]], undef
16; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt <2 x i16> [[TMP1]], splat (i16 8)
17; CHECK-NEXT:    br label [[BB25]]
18; CHECK:       bb11:
19; CHECK-NEXT:    [[I12:%.*]] = zext i1 undef to i32
20; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i16> [[TMP0]], undef
21; CHECK-NEXT:    [[TMP4:%.*]] = sext <2 x i16> [[TMP3]] to <2 x i64>
22; CHECK-NEXT:    [[TMP5:%.*]] = icmp ule <2 x i64> undef, [[TMP4]]
23; CHECK-NEXT:    [[TMP6:%.*]] = zext <2 x i1> [[TMP5]] to <2 x i32>
24; CHECK-NEXT:    [[TMP7:%.*]] = icmp ult <2 x i32> undef, [[TMP6]]
25; CHECK-NEXT:    br label [[BB25]]
26; CHECK:       bb25:
27; CHECK-NEXT:    [[I28:%.*]] = phi i32 [ [[I12]], [[BB11]] ], [ [[I4]], [[BB3]] ]
28; CHECK-NEXT:    [[TMP8:%.*]] = phi <2 x i1> [ [[TMP7]], [[BB11]] ], [ [[TMP2]], [[BB3]] ]
29; CHECK-NEXT:    [[TMP9]] = phi <2 x i16> [ [[TMP3]], [[BB11]] ], [ [[TMP1]], [[BB3]] ]
30; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0
31; CHECK-NEXT:    [[TMP11:%.*]] = zext i1 [[TMP10]] to i32
32; CHECK-NEXT:    [[I31:%.*]] = and i32 undef, [[TMP11]]
33; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1
34; CHECK-NEXT:    [[TMP13:%.*]] = zext i1 [[TMP12]] to i32
35; CHECK-NEXT:    [[I32:%.*]] = and i32 [[I31]], [[TMP13]]
36; CHECK-NEXT:    [[I33:%.*]] = and i32 [[I32]], [[I28]]
37; CHECK-NEXT:    br i1 %arg, label [[BB34:%.*]], label [[BB1]]
38; CHECK:       bb34:
39; CHECK-NEXT:    [[I35:%.*]] = phi i32 [ [[I33]], [[BB25]] ]
40; CHECK-NEXT:    br label [[BB36:%.*]]
41; CHECK:       bb36:
42; CHECK-NEXT:    store i32 [[I35]], ptr @d, align 4
43; CHECK-NEXT:    ret void
44;
45bb:
46  br label %bb1
47
48bb1:                                              ; preds = %bb25, %bb
49  %i = phi i16 [ undef, %bb ], [ %i29, %bb25 ]
50  %i2 = phi i16 [ undef, %bb ], [ %i30, %bb25 ]
51  br i1 %arg, label %bb3, label %bb11
52
53bb3:                                              ; preds = %bb1
54  %i4 = zext i1 undef to i32
55  %i5 = xor i16 %i2, undef
56  %i6 = icmp ugt i16 %i5, 8
57  %i7 = zext i1 %i6 to i32
58  %i8 = xor i16 %i, undef
59  %i9 = icmp ugt i16 %i8, 8
60  %i10 = zext i1 %i9 to i32
61  br label %bb25
62
63bb11:                                             ; preds = %bb1
64  %i12 = zext i1 undef to i32
65  %i13 = xor i16 %i2, undef
66  %i14 = sext i16 %i13 to i64
67  %i15 = icmp ule i64 undef, %i14
68  %i16 = zext i1 %i15 to i32
69  %i17 = icmp ult i32 undef, %i16
70  %i18 = zext i1 %i17 to i32
71  %i19 = xor i16 %i, undef
72  %i20 = sext i16 %i19 to i64
73  %i21 = icmp ule i64 undef, %i20
74  %i22 = zext i1 %i21 to i32
75  %i23 = icmp ult i32 undef, %i22
76  %i24 = zext i1 %i23 to i32
77  br label %bb25
78
79bb25:                                             ; preds = %bb11, %bb3
80  %i26 = phi i32 [ %i24, %bb11 ], [ %i10, %bb3 ]
81  %i27 = phi i32 [ %i18, %bb11 ], [ %i7, %bb3 ]
82  %i28 = phi i32 [ %i12, %bb11 ], [ %i4, %bb3 ]
83  %i29 = phi i16 [ %i19, %bb11 ], [ %i8, %bb3 ]
84  %i30 = phi i16 [ %i13, %bb11 ], [ %i5, %bb3 ]
85  %i31 = and i32 undef, %i26
86  %i32 = and i32 %i31, %i27
87  %i33 = and i32 %i32, %i28
88  br i1 %arg, label %bb34, label %bb1
89
90bb34:                                             ; preds = %bb25
91  %i35 = phi i32 [ %i33, %bb25 ]
92  br label %bb36
93
94bb36:                                             ; preds = %bb34
95  store i32 %i35, ptr @d, align 4
96  ret void
97}
98