1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -mtriple=arm64-apple-ios -S -passes=slp-vectorizer < %s | FileCheck %s 3 4; fshl instruction cost model is an overestimate causing this test to vectorize when it is not beneficial to do so. 5define i64 @fshl(i64 %or1, i64 %or2, i64 %or3 ) { 6; CHECK-LABEL: define i64 @fshl 7; CHECK-SAME: (i64 [[OR1:%.*]], i64 [[OR2:%.*]], i64 [[OR3:%.*]]) { 8; CHECK-NEXT: entry: 9; CHECK-NEXT: [[OR4:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[OR2]], i64 0, i64 1) 10; CHECK-NEXT: [[XOR1:%.*]] = xor i64 [[OR4]], 0 11; CHECK-NEXT: [[OR5:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[OR3]], i64 0, i64 2) 12; CHECK-NEXT: [[XOR2:%.*]] = xor i64 [[OR5]], [[OR1]] 13; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[XOR1]], [[OR1]] 14; CHECK-NEXT: [[ADD2:%.*]] = add i64 0, [[XOR2]] 15; CHECK-NEXT: [[OR6:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[OR1]], i64 [[OR2]], i64 17) 16; CHECK-NEXT: [[XOR3:%.*]] = xor i64 [[OR6]], [[ADD1]] 17; CHECK-NEXT: [[OR7:%.*]] = tail call i64 @llvm.fshl.i64(i64 0, i64 0, i64 21) 18; CHECK-NEXT: [[XOR4:%.*]] = xor i64 [[OR7]], [[ADD2]] 19; CHECK-NEXT: [[ADD3:%.*]] = or i64 [[XOR3]], [[ADD2]] 20; CHECK-NEXT: [[XOR5:%.*]] = xor i64 [[ADD3]], [[XOR4]] 21; CHECK-NEXT: ret i64 [[XOR5]] 22; 23entry: 24 %or4 = tail call i64 @llvm.fshl.i64(i64 %or2, i64 0, i64 1) 25 %xor1 = xor i64 %or4, 0 26 %or5 = tail call i64 @llvm.fshl.i64(i64 %or3, i64 0, i64 2) 27 %xor2 = xor i64 %or5, %or1 28 %add1 = add i64 %xor1, %or1 29 %add2 = add i64 0, %xor2 30 %or6 = tail call i64 @llvm.fshl.i64(i64 %or1, i64 %or2, i64 17) 31 %xor3 = xor i64 %or6, %add1 32 %or7 = tail call i64 @llvm.fshl.i64(i64 0, i64 0, i64 21) 33 %xor4 = xor i64 %or7, %add2 34 %add3 = or i64 %xor3, %add2 35 %xor5 = xor i64 %add3, %xor4 36 ret i64 %xor5 37} 38 39declare i64 @llvm.fshl.i64(i64, i64, i64) 40