xref: /llvm-project/llvm/test/Transforms/SCCP/pr52253.ll (revision 8ebb3eac02a926ffa4298c12834c57aefb2e8579) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=sccp -S | FileCheck %s
3
4define i1 @foo(i32 %t4, i32 %t10) {
5; CHECK-LABEL: @foo(
6; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
7; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
8; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
9; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
10; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
11; CHECK-NEXT:    [[T14:%.*]] = zext i1 [[T12]] to i32
12; CHECK-NEXT:    [[T15:%.*]] = shl i32 [[T4]], [[T14]]
13; CHECK-NEXT:    [[T17:%.*]] = and i32 [[T15]], 255
14; CHECK-NEXT:    ret i1 false
15;
16  %t09 = shl i32 %t10, 24
17  %t010 = ashr exact i32 %t09, 24
18  %t011 = add nsw i32 %t010, 979
19  %t11 = trunc i32 %t4 to i8
20  %t12 = icmp eq i8 %t11, 0
21  %t14 = zext i1 %t12 to i32
22  %t15 = shl i32 %t4, %t14
23  %t17 = and i32 %t15, 255
24  %t18 = icmp eq i32 %t011, %t17
25  ret i1 %t18
26}
27
28define i1 @bar(i32 %t4, i32 %t10) {
29; CHECK-LABEL: @bar(
30; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
31; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
32; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
33; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
34; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
35; CHECK-NEXT:    [[T14:%.*]] = zext i1 [[T12]] to i8
36; CHECK-NEXT:    [[T15:%.*]] = shl i8 [[T11]], [[T14]]
37; CHECK-NEXT:    [[T17:%.*]] = zext i8 [[T15]] to i32
38; CHECK-NEXT:    ret i1 false
39;
40  %t09 = shl i32 %t10, 24
41  %t010 = ashr exact i32 %t09, 24
42  %t011 = add nsw i32 %t010, 979
43  %t11 = trunc i32 %t4 to i8
44  %t12 = icmp eq i8 %t11, 0
45  %t14 = zext i1 %t12 to i8
46  %t15 = shl i8 %t11, %t14
47  %t17 = zext i8 %t15 to i32
48  %t18 = icmp eq i32 %t011, %t17
49  ret i1 %t18
50}
51
52define i1 @foobar(i32 %t4, i32 %t10) {
53; CHECK-LABEL: @foobar(
54; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
55; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
56; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
57; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
58; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
59; CHECK-NEXT:    [[T13:%.*]] = zext i8 [[T11]] to i32
60; CHECK-NEXT:    [[T14:%.*]] = select i1 [[T12]], i32 1, i32 0
61; CHECK-NEXT:    [[T15:%.*]] = shl nuw nsw i32 [[T13]], [[T14]]
62; CHECK-NEXT:    [[T16:%.*]] = trunc i32 [[T15]] to i8
63; CHECK-NEXT:    [[T17:%.*]] = zext i8 [[T16]] to i32
64; CHECK-NEXT:    ret i1 false
65;
66  %t09 = shl i32 %t10, 24
67  %t010 = ashr exact i32 %t09, 24
68  %t011 = add nsw i32 %t010, 979
69
70  %t11 = trunc i32 %t4 to i8
71  %t12 = icmp eq i8 %t11, 0
72  %t13 = zext i8 %t11 to i32
73  %t14 = select i1 %t12, i32 1, i32 0
74  %t15 = shl nuw nsw i32 %t13, %t14
75  %t16 = trunc i32 %t15 to i8
76  %t17 = zext i8 %t16 to i32
77
78  %t18 = icmp eq i32 %t011, %t17
79  ret i1 %t18
80}
81