xref: /llvm-project/llvm/test/Transforms/PhaseOrdering/srem.ll (revision 85b289377bff14790f402e5ea84bb24168a68fc6)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -O1 -S < %s | FileCheck %s
3; RUN: opt -O2 -S < %s | FileCheck %s
4; RUN: opt -O3 -S < %s | FileCheck %s
5
6; srem should be folded based on branch conditions
7; This can be done by IPSCCP or CVP.
8
9define i32 @PR57472(i32 noundef %x) {
10; CHECK-LABEL: @PR57472(
11; CHECK-NEXT:  entry:
12; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
13; CHECK-NEXT:    [[REM:%.*]] = and i32 [[X]], 15
14; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[REM]], i32 42
15; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
16;
17entry:
18  %x.addr = alloca i32, align 4
19  store i32 %x, ptr %x.addr, align 4
20  %0 = load i32, ptr %x.addr, align 4
21  %cmp = icmp sge i32 %0, 0
22  br i1 %cmp, label %cond.true, label %cond.false
23
24cond.true:
25  %1 = load i32, ptr %x.addr, align 4
26  %rem = srem i32 %1, 16
27  br label %cond.end
28
29cond.false:
30  br label %cond.end
31
32cond.end:
33  %cond = phi i32 [ %rem, %cond.true ], [ 42, %cond.false ]
34  ret i32 %cond
35}
36