1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s 3 4define i64 @PR36760(i64 %a) { 5; CHECK-LABEL: @PR36760( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.smax.i64(i64 [[A:%.*]], i64 0) 8; CHECK-NEXT: ret i64 [[TMP0]] 9; 10entry: 11 %retval = alloca i64, align 8 12 %a.addr = alloca i64, align 8 13 store i64 %a, ptr %a.addr, align 8 14 %0 = load i64, ptr %a.addr, align 8 15 %cmp = icmp slt i64 %0, 0 16 br i1 %cmp, label %if.then, label %if.end 17 18if.then: 19 store i64 0, ptr %retval, align 8 20 br label %return 21 22if.end: 23 %1 = load i64, ptr %a.addr, align 8 24 %shr = ashr i64 %1, 63 25 %2 = load i64, ptr %a.addr, align 8 26 %xor = xor i64 %shr, %2 27 store i64 %xor, ptr %retval, align 8 28 br label %return 29 30return: 31 %3 = load i64, ptr %retval, align 8 32 ret i64 %3 33} 34 35define i64 @PR36760_2(i64 %a) #0 { 36; CHECK-LABEL: @PR36760_2( 37; CHECK-NEXT: entry: 38; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.smin.i64(i64 [[A:%.*]], i64 -1) 39; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], -1 40; CHECK-NEXT: ret i64 [[TMP1]] 41; 42entry: 43 %retval = alloca i64, align 8 44 %a.addr = alloca i64, align 8 45 store i64 %a, ptr %a.addr, align 8 46 %0 = load i64, ptr %a.addr, align 8 47 %cmp = icmp sge i64 %0, 0 48 br i1 %cmp, label %if.then, label %if.end 49 50if.then: ; preds = %entry 51 store i64 0, ptr %retval, align 8 52 br label %return 53 54if.end: ; preds = %entry 55 %1 = load i64, ptr %a.addr, align 8 56 %shr = ashr i64 %1, 63 57 %2 = load i64, ptr %a.addr, align 8 58 %xor = xor i64 %shr, %2 59 store i64 %xor, ptr %retval, align 8 60 br label %return 61 62return: ; preds = %if.end, %if.then 63 %3 = load i64, ptr %retval, align 8 64 ret i64 %3 65} 66