xref: /llvm-project/llvm/test/Transforms/PhaseOrdering/X86/pr52078.ll (revision 70dc3b811e4926fa2c88bd3b53b29c46fcba1a90)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -O2 -S < %s | FileCheck %s
3; RUN: opt -passes=instcombine -S < %s | FileCheck %s --check-prefix=IC
4; RUN: opt -passes=aggressive-instcombine,instcombine -S < %s | FileCheck %s --check-prefix=AIC_AND_IC
5
6target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
7target triple = "x86_64-unknown-linux-gnu"
8
9define i16 @foo(i1 %a) {
10; CHECK-LABEL: @foo(
11; CHECK-NEXT:    [[TRUNC:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
12; CHECK-NEXT:    ret i16 [[TRUNC]]
13;
14; IC-LABEL: @foo(
15; IC-NEXT:    [[TRUNC:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
16; IC-NEXT:    ret i16 [[TRUNC]]
17;
18; AIC_AND_IC-LABEL: @foo(
19; AIC_AND_IC-NEXT:    [[LSHR:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
20; AIC_AND_IC-NEXT:    ret i16 [[LSHR]]
21;
22  %sext = sext i1 %a to i16
23  %zext = zext i16 %sext to i32
24  %lshr = lshr i32 %zext, 1
25  %trunc = trunc i32 %lshr to i16
26  ret i16 %trunc
27}
28
29define i16 @foo2(i1 %a) {
30; CHECK-LABEL: @foo2(
31; CHECK-NEXT:    [[LSHR:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
32; CHECK-NEXT:    ret i16 [[LSHR]]
33;
34; IC-LABEL: @foo2(
35; IC-NEXT:    [[LSHR:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
36; IC-NEXT:    ret i16 [[LSHR]]
37;
38; AIC_AND_IC-LABEL: @foo2(
39; AIC_AND_IC-NEXT:    [[LSHR:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
40; AIC_AND_IC-NEXT:    ret i16 [[LSHR]]
41;
42  %s = sext i1 %a to i16
43  %lshr = lshr i16 %s, 1
44  ret i16 %lshr
45}
46