1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -S -O3 < %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5target triple = "aarch64" 6 7; Check that the function gets vectorized. 8 9define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { 10; CHECK-LABEL: define range(i32 0, 2) i32 @quant_4x4 11; CHECK-SAME: (ptr noundef captures(none) [[DCT:%.*]], ptr noundef readonly captures(none) [[MF:%.*]], ptr noundef readonly captures(none) [[BIAS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { 12; CHECK-NEXT: entry: 13; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DCT]], i64 32 14; CHECK-NEXT: [[SCEVGEP23:%.*]] = getelementptr i8, ptr [[BIAS]], i64 32 15; CHECK-NEXT: [[SCEVGEP24:%.*]] = getelementptr i8, ptr [[MF]], i64 32 16; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP23]] 17; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BIAS]], [[SCEVGEP]] 18; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 19; CHECK-NEXT: [[BOUND025:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP24]] 20; CHECK-NEXT: [[BOUND126:%.*]] = icmp ult ptr [[MF]], [[SCEVGEP]] 21; CHECK-NEXT: [[FOUND_CONFLICT27:%.*]] = and i1 [[BOUND025]], [[BOUND126]] 22; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT27]] 23; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]] 24; CHECK: vector.body: 25; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 16 26; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[DCT]], align 2, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]] 27; CHECK-NEXT: [[WIDE_LOAD29:%.*]] = load <8 x i16>, ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]] 28; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32> 29; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[WIDE_LOAD29]] to <8 x i32> 30; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer 31; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD29]], zeroinitializer 32; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 16 33; CHECK-NEXT: [[WIDE_LOAD30:%.*]] = load <8 x i16>, ptr [[BIAS]], align 2, !alias.scope [[META6:![0-9]+]] 34; CHECK-NEXT: [[WIDE_LOAD31:%.*]] = load <8 x i16>, ptr [[TMP5]], align 2, !alias.scope [[META6]] 35; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i16> [[WIDE_LOAD30]] to <8 x i32> 36; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i16> [[WIDE_LOAD31]] to <8 x i32> 37; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 16 38; CHECK-NEXT: [[WIDE_LOAD32:%.*]] = load <8 x i16>, ptr [[MF]], align 2, !alias.scope [[META7:![0-9]+]] 39; CHECK-NEXT: [[WIDE_LOAD33:%.*]] = load <8 x i16>, ptr [[TMP8]], align 2, !alias.scope [[META7]] 40; CHECK-NEXT: [[TMP9:%.*]] = zext <8 x i16> [[WIDE_LOAD32]] to <8 x i32> 41; CHECK-NEXT: [[TMP10:%.*]] = zext <8 x i16> [[WIDE_LOAD33]] to <8 x i32> 42; CHECK-NEXT: [[TMP11:%.*]] = sub nsw <8 x i32> [[TMP6]], [[TMP1]] 43; CHECK-NEXT: [[TMP12:%.*]] = sub nsw <8 x i32> [[TMP7]], [[TMP2]] 44; CHECK-NEXT: [[TMP13:%.*]] = mul <8 x i32> [[TMP11]], [[TMP9]] 45; CHECK-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP12]], [[TMP10]] 46; CHECK-NEXT: [[TMP15:%.*]] = lshr <8 x i32> [[TMP13]], splat (i32 16) 47; CHECK-NEXT: [[TMP16:%.*]] = lshr <8 x i32> [[TMP14]], splat (i32 16) 48; CHECK-NEXT: [[TMP17:%.*]] = trunc nuw <8 x i32> [[TMP15]] to <8 x i16> 49; CHECK-NEXT: [[TMP18:%.*]] = trunc nuw <8 x i32> [[TMP16]] to <8 x i16> 50; CHECK-NEXT: [[TMP19:%.*]] = sub <8 x i16> zeroinitializer, [[TMP17]] 51; CHECK-NEXT: [[TMP20:%.*]] = sub <8 x i16> zeroinitializer, [[TMP18]] 52; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw <8 x i32> [[TMP6]], [[TMP1]] 53; CHECK-NEXT: [[TMP22:%.*]] = add nuw nsw <8 x i32> [[TMP7]], [[TMP2]] 54; CHECK-NEXT: [[TMP23:%.*]] = mul <8 x i32> [[TMP21]], [[TMP9]] 55; CHECK-NEXT: [[TMP24:%.*]] = mul <8 x i32> [[TMP22]], [[TMP10]] 56; CHECK-NEXT: [[TMP25:%.*]] = lshr <8 x i32> [[TMP23]], splat (i32 16) 57; CHECK-NEXT: [[TMP26:%.*]] = lshr <8 x i32> [[TMP24]], splat (i32 16) 58; CHECK-NEXT: [[TMP27:%.*]] = trunc nuw <8 x i32> [[TMP25]] to <8 x i16> 59; CHECK-NEXT: [[TMP28:%.*]] = trunc nuw <8 x i32> [[TMP26]] to <8 x i16> 60; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP27]], <8 x i16> [[TMP19]] 61; CHECK-NEXT: [[PREDPHI34:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP28]], <8 x i16> [[TMP20]] 62; CHECK-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope [[META0]], !noalias [[META3]] 63; CHECK-NEXT: store <8 x i16> [[PREDPHI34]], ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]] 64; CHECK-NEXT: [[BIN_RDX35:%.*]] = or <8 x i16> [[PREDPHI34]], [[PREDPHI]] 65; CHECK-NEXT: [[BIN_RDX:%.*]] = sext <8 x i16> [[BIN_RDX35]] to <8 x i32> 66; CHECK-NEXT: [[TMP29:%.*]] = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[BIN_RDX]]) 67; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]] 68; CHECK: for.cond.cleanup: 69; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i32 [ [[TMP29]], [[VECTOR_BODY]] ], [ [[OR_15:%.*]], [[IF_END_15:%.*]] ] 70; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR_LCSSA]], 0 71; CHECK-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL]] to i32 72; CHECK-NEXT: ret i32 [[LNOT_EXT]] 73; CHECK: for.body: 74; CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[DCT]], align 2 75; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP30]] to i32 76; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP30]], 0 77; CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[BIAS]], align 2 78; CHECK-NEXT: [[CONV5:%.*]] = zext i16 [[TMP31]] to i32 79; CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[MF]], align 2 80; CHECK-NEXT: [[CONV11:%.*]] = zext i16 [[TMP32]] to i32 81; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] 82; CHECK: if.then: 83; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV5]], [[CONV]] 84; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ADD]], [[CONV11]] 85; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 16 86; CHECK-NEXT: [[CONV12:%.*]] = trunc nuw i32 [[SHR]] to i16 87; CHECK-NEXT: br label [[IF_END:%.*]] 88; CHECK: if.else: 89; CHECK-NEXT: [[ADD21:%.*]] = sub nsw i32 [[CONV5]], [[CONV]] 90; CHECK-NEXT: [[MUL25:%.*]] = mul i32 [[ADD21]], [[CONV11]] 91; CHECK-NEXT: [[SHR26:%.*]] = lshr i32 [[MUL25]], 16 92; CHECK-NEXT: [[TMP33:%.*]] = trunc nuw i32 [[SHR26]] to i16 93; CHECK-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP33]] 94; CHECK-NEXT: br label [[IF_END]] 95; CHECK: if.end: 96; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i16 [ [[CONV28]], [[IF_ELSE]] ], [ [[CONV12]], [[IF_THEN]] ] 97; CHECK-NEXT: store i16 [[STOREMERGE]], ptr [[DCT]], align 2 98; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 2 99; CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 2 100; CHECK-NEXT: [[CONV_1:%.*]] = sext i16 [[TMP34]] to i32 101; CHECK-NEXT: [[CMP1_1:%.*]] = icmp sgt i16 [[TMP34]], 0 102; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 2 103; CHECK-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX4_1]], align 2 104; CHECK-NEXT: [[CONV5_1:%.*]] = zext i16 [[TMP35]] to i32 105; CHECK-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 2 106; CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[ARRAYIDX10_1]], align 2 107; CHECK-NEXT: [[CONV11_1:%.*]] = zext i16 [[TMP36]] to i32 108; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]] 109; CHECK: if.else.1: 110; CHECK-NEXT: [[ADD21_1:%.*]] = sub nsw i32 [[CONV5_1]], [[CONV_1]] 111; CHECK-NEXT: [[MUL25_1:%.*]] = mul i32 [[ADD21_1]], [[CONV11_1]] 112; CHECK-NEXT: [[SHR26_1:%.*]] = lshr i32 [[MUL25_1]], 16 113; CHECK-NEXT: [[TMP37:%.*]] = trunc nuw i32 [[SHR26_1]] to i16 114; CHECK-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP37]] 115; CHECK-NEXT: br label [[IF_END_1:%.*]] 116; CHECK: if.then.1: 117; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[CONV5_1]], [[CONV_1]] 118; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[ADD_1]], [[CONV11_1]] 119; CHECK-NEXT: [[SHR_1:%.*]] = lshr i32 [[MUL_1]], 16 120; CHECK-NEXT: [[CONV12_1:%.*]] = trunc nuw i32 [[SHR_1]] to i16 121; CHECK-NEXT: br label [[IF_END_1]] 122; CHECK: if.end.1: 123; CHECK-NEXT: [[STOREMERGE_1:%.*]] = phi i16 [ [[CONV28_1]], [[IF_ELSE_1]] ], [ [[CONV12_1]], [[IF_THEN_1]] ] 124; CHECK-NEXT: store i16 [[STOREMERGE_1]], ptr [[ARRAYIDX_1]], align 2 125; CHECK-NEXT: [[OR_137:%.*]] = or i16 [[STOREMERGE]], [[STOREMERGE_1]] 126; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 4 127; CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 2 128; CHECK-NEXT: [[CONV_2:%.*]] = sext i16 [[TMP38]] to i32 129; CHECK-NEXT: [[CMP1_2:%.*]] = icmp sgt i16 [[TMP38]], 0 130; CHECK-NEXT: [[ARRAYIDX4_2:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 4 131; CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[ARRAYIDX4_2]], align 2 132; CHECK-NEXT: [[CONV5_2:%.*]] = zext i16 [[TMP39]] to i32 133; CHECK-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 4 134; CHECK-NEXT: [[TMP40:%.*]] = load i16, ptr [[ARRAYIDX10_2]], align 2 135; CHECK-NEXT: [[CONV11_2:%.*]] = zext i16 [[TMP40]] to i32 136; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]] 137; CHECK: if.else.2: 138; CHECK-NEXT: [[ADD21_2:%.*]] = sub nsw i32 [[CONV5_2]], [[CONV_2]] 139; CHECK-NEXT: [[MUL25_2:%.*]] = mul i32 [[ADD21_2]], [[CONV11_2]] 140; CHECK-NEXT: [[SHR26_2:%.*]] = lshr i32 [[MUL25_2]], 16 141; CHECK-NEXT: [[TMP41:%.*]] = trunc nuw i32 [[SHR26_2]] to i16 142; CHECK-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP41]] 143; CHECK-NEXT: br label [[IF_END_2:%.*]] 144; CHECK: if.then.2: 145; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[CONV5_2]], [[CONV_2]] 146; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[ADD_2]], [[CONV11_2]] 147; CHECK-NEXT: [[SHR_2:%.*]] = lshr i32 [[MUL_2]], 16 148; CHECK-NEXT: [[CONV12_2:%.*]] = trunc nuw i32 [[SHR_2]] to i16 149; CHECK-NEXT: br label [[IF_END_2]] 150; CHECK: if.end.2: 151; CHECK-NEXT: [[STOREMERGE_2:%.*]] = phi i16 [ [[CONV28_2]], [[IF_ELSE_2]] ], [ [[CONV12_2]], [[IF_THEN_2]] ] 152; CHECK-NEXT: store i16 [[STOREMERGE_2]], ptr [[ARRAYIDX_2]], align 2 153; CHECK-NEXT: [[OR_238:%.*]] = or i16 [[OR_137]], [[STOREMERGE_2]] 154; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 6 155; CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 2 156; CHECK-NEXT: [[CONV_3:%.*]] = sext i16 [[TMP42]] to i32 157; CHECK-NEXT: [[CMP1_3:%.*]] = icmp sgt i16 [[TMP42]], 0 158; CHECK-NEXT: [[ARRAYIDX4_3:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 6 159; CHECK-NEXT: [[TMP43:%.*]] = load i16, ptr [[ARRAYIDX4_3]], align 2 160; CHECK-NEXT: [[CONV5_3:%.*]] = zext i16 [[TMP43]] to i32 161; CHECK-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 6 162; CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX10_3]], align 2 163; CHECK-NEXT: [[CONV11_3:%.*]] = zext i16 [[TMP44]] to i32 164; CHECK-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]] 165; CHECK: if.else.3: 166; CHECK-NEXT: [[ADD21_3:%.*]] = sub nsw i32 [[CONV5_3]], [[CONV_3]] 167; CHECK-NEXT: [[MUL25_3:%.*]] = mul i32 [[ADD21_3]], [[CONV11_3]] 168; CHECK-NEXT: [[SHR26_3:%.*]] = lshr i32 [[MUL25_3]], 16 169; CHECK-NEXT: [[TMP45:%.*]] = trunc nuw i32 [[SHR26_3]] to i16 170; CHECK-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP45]] 171; CHECK-NEXT: br label [[IF_END_3:%.*]] 172; CHECK: if.then.3: 173; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[CONV5_3]], [[CONV_3]] 174; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[ADD_3]], [[CONV11_3]] 175; CHECK-NEXT: [[SHR_3:%.*]] = lshr i32 [[MUL_3]], 16 176; CHECK-NEXT: [[CONV12_3:%.*]] = trunc nuw i32 [[SHR_3]] to i16 177; CHECK-NEXT: br label [[IF_END_3]] 178; CHECK: if.end.3: 179; CHECK-NEXT: [[STOREMERGE_3:%.*]] = phi i16 [ [[CONV28_3]], [[IF_ELSE_3]] ], [ [[CONV12_3]], [[IF_THEN_3]] ] 180; CHECK-NEXT: store i16 [[STOREMERGE_3]], ptr [[ARRAYIDX_3]], align 2 181; CHECK-NEXT: [[OR_339:%.*]] = or i16 [[OR_238]], [[STOREMERGE_3]] 182; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 8 183; CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2 184; CHECK-NEXT: [[CONV_4:%.*]] = sext i16 [[TMP46]] to i32 185; CHECK-NEXT: [[CMP1_4:%.*]] = icmp sgt i16 [[TMP46]], 0 186; CHECK-NEXT: [[ARRAYIDX4_4:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 8 187; CHECK-NEXT: [[TMP47:%.*]] = load i16, ptr [[ARRAYIDX4_4]], align 2 188; CHECK-NEXT: [[CONV5_4:%.*]] = zext i16 [[TMP47]] to i32 189; CHECK-NEXT: [[ARRAYIDX10_4:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 8 190; CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[ARRAYIDX10_4]], align 2 191; CHECK-NEXT: [[CONV11_4:%.*]] = zext i16 [[TMP48]] to i32 192; CHECK-NEXT: br i1 [[CMP1_4]], label [[IF_THEN_4:%.*]], label [[IF_ELSE_4:%.*]] 193; CHECK: if.else.4: 194; CHECK-NEXT: [[ADD21_4:%.*]] = sub nsw i32 [[CONV5_4]], [[CONV_4]] 195; CHECK-NEXT: [[MUL25_4:%.*]] = mul i32 [[ADD21_4]], [[CONV11_4]] 196; CHECK-NEXT: [[SHR26_4:%.*]] = lshr i32 [[MUL25_4]], 16 197; CHECK-NEXT: [[TMP49:%.*]] = trunc nuw i32 [[SHR26_4]] to i16 198; CHECK-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP49]] 199; CHECK-NEXT: br label [[IF_END_4:%.*]] 200; CHECK: if.then.4: 201; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[CONV5_4]], [[CONV_4]] 202; CHECK-NEXT: [[MUL_4:%.*]] = mul i32 [[ADD_4]], [[CONV11_4]] 203; CHECK-NEXT: [[SHR_4:%.*]] = lshr i32 [[MUL_4]], 16 204; CHECK-NEXT: [[CONV12_4:%.*]] = trunc nuw i32 [[SHR_4]] to i16 205; CHECK-NEXT: br label [[IF_END_4]] 206; CHECK: if.end.4: 207; CHECK-NEXT: [[STOREMERGE_4:%.*]] = phi i16 [ [[CONV28_4]], [[IF_ELSE_4]] ], [ [[CONV12_4]], [[IF_THEN_4]] ] 208; CHECK-NEXT: store i16 [[STOREMERGE_4]], ptr [[ARRAYIDX_4]], align 2 209; CHECK-NEXT: [[OR_440:%.*]] = or i16 [[OR_339]], [[STOREMERGE_4]] 210; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 10 211; CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2 212; CHECK-NEXT: [[CONV_5:%.*]] = sext i16 [[TMP50]] to i32 213; CHECK-NEXT: [[CMP1_5:%.*]] = icmp sgt i16 [[TMP50]], 0 214; CHECK-NEXT: [[ARRAYIDX4_5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 10 215; CHECK-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4_5]], align 2 216; CHECK-NEXT: [[CONV5_5:%.*]] = zext i16 [[TMP51]] to i32 217; CHECK-NEXT: [[ARRAYIDX10_5:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 10 218; CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[ARRAYIDX10_5]], align 2 219; CHECK-NEXT: [[CONV11_5:%.*]] = zext i16 [[TMP52]] to i32 220; CHECK-NEXT: br i1 [[CMP1_5]], label [[IF_THEN_5:%.*]], label [[IF_ELSE_5:%.*]] 221; CHECK: if.else.5: 222; CHECK-NEXT: [[ADD21_5:%.*]] = sub nsw i32 [[CONV5_5]], [[CONV_5]] 223; CHECK-NEXT: [[MUL25_5:%.*]] = mul i32 [[ADD21_5]], [[CONV11_5]] 224; CHECK-NEXT: [[SHR26_5:%.*]] = lshr i32 [[MUL25_5]], 16 225; CHECK-NEXT: [[TMP53:%.*]] = trunc nuw i32 [[SHR26_5]] to i16 226; CHECK-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP53]] 227; CHECK-NEXT: br label [[IF_END_5:%.*]] 228; CHECK: if.then.5: 229; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[CONV5_5]], [[CONV_5]] 230; CHECK-NEXT: [[MUL_5:%.*]] = mul i32 [[ADD_5]], [[CONV11_5]] 231; CHECK-NEXT: [[SHR_5:%.*]] = lshr i32 [[MUL_5]], 16 232; CHECK-NEXT: [[CONV12_5:%.*]] = trunc nuw i32 [[SHR_5]] to i16 233; CHECK-NEXT: br label [[IF_END_5]] 234; CHECK: if.end.5: 235; CHECK-NEXT: [[STOREMERGE_5:%.*]] = phi i16 [ [[CONV28_5]], [[IF_ELSE_5]] ], [ [[CONV12_5]], [[IF_THEN_5]] ] 236; CHECK-NEXT: store i16 [[STOREMERGE_5]], ptr [[ARRAYIDX_5]], align 2 237; CHECK-NEXT: [[OR_541:%.*]] = or i16 [[OR_440]], [[STOREMERGE_5]] 238; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 12 239; CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2 240; CHECK-NEXT: [[CONV_6:%.*]] = sext i16 [[TMP54]] to i32 241; CHECK-NEXT: [[CMP1_6:%.*]] = icmp sgt i16 [[TMP54]], 0 242; CHECK-NEXT: [[ARRAYIDX4_6:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 12 243; CHECK-NEXT: [[TMP55:%.*]] = load i16, ptr [[ARRAYIDX4_6]], align 2 244; CHECK-NEXT: [[CONV5_6:%.*]] = zext i16 [[TMP55]] to i32 245; CHECK-NEXT: [[ARRAYIDX10_6:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 12 246; CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[ARRAYIDX10_6]], align 2 247; CHECK-NEXT: [[CONV11_6:%.*]] = zext i16 [[TMP56]] to i32 248; CHECK-NEXT: br i1 [[CMP1_6]], label [[IF_THEN_6:%.*]], label [[IF_ELSE_6:%.*]] 249; CHECK: if.else.6: 250; CHECK-NEXT: [[ADD21_6:%.*]] = sub nsw i32 [[CONV5_6]], [[CONV_6]] 251; CHECK-NEXT: [[MUL25_6:%.*]] = mul i32 [[ADD21_6]], [[CONV11_6]] 252; CHECK-NEXT: [[SHR26_6:%.*]] = lshr i32 [[MUL25_6]], 16 253; CHECK-NEXT: [[TMP57:%.*]] = trunc nuw i32 [[SHR26_6]] to i16 254; CHECK-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP57]] 255; CHECK-NEXT: br label [[IF_END_6:%.*]] 256; CHECK: if.then.6: 257; CHECK-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[CONV5_6]], [[CONV_6]] 258; CHECK-NEXT: [[MUL_6:%.*]] = mul i32 [[ADD_6]], [[CONV11_6]] 259; CHECK-NEXT: [[SHR_6:%.*]] = lshr i32 [[MUL_6]], 16 260; CHECK-NEXT: [[CONV12_6:%.*]] = trunc nuw i32 [[SHR_6]] to i16 261; CHECK-NEXT: br label [[IF_END_6]] 262; CHECK: if.end.6: 263; CHECK-NEXT: [[STOREMERGE_6:%.*]] = phi i16 [ [[CONV28_6]], [[IF_ELSE_6]] ], [ [[CONV12_6]], [[IF_THEN_6]] ] 264; CHECK-NEXT: store i16 [[STOREMERGE_6]], ptr [[ARRAYIDX_6]], align 2 265; CHECK-NEXT: [[OR_642:%.*]] = or i16 [[OR_541]], [[STOREMERGE_6]] 266; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 14 267; CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2 268; CHECK-NEXT: [[CONV_7:%.*]] = sext i16 [[TMP58]] to i32 269; CHECK-NEXT: [[CMP1_7:%.*]] = icmp sgt i16 [[TMP58]], 0 270; CHECK-NEXT: [[ARRAYIDX4_7:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 14 271; CHECK-NEXT: [[TMP59:%.*]] = load i16, ptr [[ARRAYIDX4_7]], align 2 272; CHECK-NEXT: [[CONV5_7:%.*]] = zext i16 [[TMP59]] to i32 273; CHECK-NEXT: [[ARRAYIDX10_7:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 14 274; CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[ARRAYIDX10_7]], align 2 275; CHECK-NEXT: [[CONV11_7:%.*]] = zext i16 [[TMP60]] to i32 276; CHECK-NEXT: br i1 [[CMP1_7]], label [[IF_THEN_7:%.*]], label [[IF_ELSE_7:%.*]] 277; CHECK: if.else.7: 278; CHECK-NEXT: [[ADD21_7:%.*]] = sub nsw i32 [[CONV5_7]], [[CONV_7]] 279; CHECK-NEXT: [[MUL25_7:%.*]] = mul i32 [[ADD21_7]], [[CONV11_7]] 280; CHECK-NEXT: [[SHR26_7:%.*]] = lshr i32 [[MUL25_7]], 16 281; CHECK-NEXT: [[TMP61:%.*]] = trunc nuw i32 [[SHR26_7]] to i16 282; CHECK-NEXT: [[CONV28_7:%.*]] = sub i16 0, [[TMP61]] 283; CHECK-NEXT: br label [[IF_END_7:%.*]] 284; CHECK: if.then.7: 285; CHECK-NEXT: [[ADD_7:%.*]] = add nuw nsw i32 [[CONV5_7]], [[CONV_7]] 286; CHECK-NEXT: [[MUL_7:%.*]] = mul i32 [[ADD_7]], [[CONV11_7]] 287; CHECK-NEXT: [[SHR_7:%.*]] = lshr i32 [[MUL_7]], 16 288; CHECK-NEXT: [[CONV12_7:%.*]] = trunc nuw i32 [[SHR_7]] to i16 289; CHECK-NEXT: br label [[IF_END_7]] 290; CHECK: if.end.7: 291; CHECK-NEXT: [[STOREMERGE_7:%.*]] = phi i16 [ [[CONV28_7]], [[IF_ELSE_7]] ], [ [[CONV12_7]], [[IF_THEN_7]] ] 292; CHECK-NEXT: store i16 [[STOREMERGE_7]], ptr [[ARRAYIDX_7]], align 2 293; CHECK-NEXT: [[OR_743:%.*]] = or i16 [[OR_642]], [[STOREMERGE_7]] 294; CHECK-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 16 295; CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[ARRAYIDX_8]], align 2 296; CHECK-NEXT: [[CONV_8:%.*]] = sext i16 [[TMP62]] to i32 297; CHECK-NEXT: [[CMP1_8:%.*]] = icmp sgt i16 [[TMP62]], 0 298; CHECK-NEXT: [[ARRAYIDX4_8:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 16 299; CHECK-NEXT: [[TMP63:%.*]] = load i16, ptr [[ARRAYIDX4_8]], align 2 300; CHECK-NEXT: [[CONV5_8:%.*]] = zext i16 [[TMP63]] to i32 301; CHECK-NEXT: [[ARRAYIDX10_8:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 16 302; CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[ARRAYIDX10_8]], align 2 303; CHECK-NEXT: [[CONV11_8:%.*]] = zext i16 [[TMP64]] to i32 304; CHECK-NEXT: br i1 [[CMP1_8]], label [[IF_THEN_8:%.*]], label [[IF_ELSE_8:%.*]] 305; CHECK: if.else.8: 306; CHECK-NEXT: [[ADD21_8:%.*]] = sub nsw i32 [[CONV5_8]], [[CONV_8]] 307; CHECK-NEXT: [[MUL25_8:%.*]] = mul i32 [[ADD21_8]], [[CONV11_8]] 308; CHECK-NEXT: [[SHR26_8:%.*]] = lshr i32 [[MUL25_8]], 16 309; CHECK-NEXT: [[TMP65:%.*]] = trunc nuw i32 [[SHR26_8]] to i16 310; CHECK-NEXT: [[CONV28_8:%.*]] = sub i16 0, [[TMP65]] 311; CHECK-NEXT: br label [[IF_END_8:%.*]] 312; CHECK: if.then.8: 313; CHECK-NEXT: [[ADD_8:%.*]] = add nuw nsw i32 [[CONV5_8]], [[CONV_8]] 314; CHECK-NEXT: [[MUL_8:%.*]] = mul i32 [[ADD_8]], [[CONV11_8]] 315; CHECK-NEXT: [[SHR_8:%.*]] = lshr i32 [[MUL_8]], 16 316; CHECK-NEXT: [[CONV12_8:%.*]] = trunc nuw i32 [[SHR_8]] to i16 317; CHECK-NEXT: br label [[IF_END_8]] 318; CHECK: if.end.8: 319; CHECK-NEXT: [[STOREMERGE_8:%.*]] = phi i16 [ [[CONV28_8]], [[IF_ELSE_8]] ], [ [[CONV12_8]], [[IF_THEN_8]] ] 320; CHECK-NEXT: store i16 [[STOREMERGE_8]], ptr [[ARRAYIDX_8]], align 2 321; CHECK-NEXT: [[OR_844:%.*]] = or i16 [[OR_743]], [[STOREMERGE_8]] 322; CHECK-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 18 323; CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[ARRAYIDX_9]], align 2 324; CHECK-NEXT: [[CONV_9:%.*]] = sext i16 [[TMP66]] to i32 325; CHECK-NEXT: [[CMP1_9:%.*]] = icmp sgt i16 [[TMP66]], 0 326; CHECK-NEXT: [[ARRAYIDX4_9:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 18 327; CHECK-NEXT: [[TMP67:%.*]] = load i16, ptr [[ARRAYIDX4_9]], align 2 328; CHECK-NEXT: [[CONV5_9:%.*]] = zext i16 [[TMP67]] to i32 329; CHECK-NEXT: [[ARRAYIDX10_9:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 18 330; CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[ARRAYIDX10_9]], align 2 331; CHECK-NEXT: [[CONV11_9:%.*]] = zext i16 [[TMP68]] to i32 332; CHECK-NEXT: br i1 [[CMP1_9]], label [[IF_THEN_9:%.*]], label [[IF_ELSE_9:%.*]] 333; CHECK: if.else.9: 334; CHECK-NEXT: [[ADD21_9:%.*]] = sub nsw i32 [[CONV5_9]], [[CONV_9]] 335; CHECK-NEXT: [[MUL25_9:%.*]] = mul i32 [[ADD21_9]], [[CONV11_9]] 336; CHECK-NEXT: [[SHR26_9:%.*]] = lshr i32 [[MUL25_9]], 16 337; CHECK-NEXT: [[TMP69:%.*]] = trunc nuw i32 [[SHR26_9]] to i16 338; CHECK-NEXT: [[CONV28_9:%.*]] = sub i16 0, [[TMP69]] 339; CHECK-NEXT: br label [[IF_END_9:%.*]] 340; CHECK: if.then.9: 341; CHECK-NEXT: [[ADD_9:%.*]] = add nuw nsw i32 [[CONV5_9]], [[CONV_9]] 342; CHECK-NEXT: [[MUL_9:%.*]] = mul i32 [[ADD_9]], [[CONV11_9]] 343; CHECK-NEXT: [[SHR_9:%.*]] = lshr i32 [[MUL_9]], 16 344; CHECK-NEXT: [[CONV12_9:%.*]] = trunc nuw i32 [[SHR_9]] to i16 345; CHECK-NEXT: br label [[IF_END_9]] 346; CHECK: if.end.9: 347; CHECK-NEXT: [[STOREMERGE_9:%.*]] = phi i16 [ [[CONV28_9]], [[IF_ELSE_9]] ], [ [[CONV12_9]], [[IF_THEN_9]] ] 348; CHECK-NEXT: store i16 [[STOREMERGE_9]], ptr [[ARRAYIDX_9]], align 2 349; CHECK-NEXT: [[OR_945:%.*]] = or i16 [[OR_844]], [[STOREMERGE_9]] 350; CHECK-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 20 351; CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[ARRAYIDX_10]], align 2 352; CHECK-NEXT: [[CONV_10:%.*]] = sext i16 [[TMP70]] to i32 353; CHECK-NEXT: [[CMP1_10:%.*]] = icmp sgt i16 [[TMP70]], 0 354; CHECK-NEXT: [[ARRAYIDX4_10:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 20 355; CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[ARRAYIDX4_10]], align 2 356; CHECK-NEXT: [[CONV5_10:%.*]] = zext i16 [[TMP71]] to i32 357; CHECK-NEXT: [[ARRAYIDX10_10:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 20 358; CHECK-NEXT: [[TMP72:%.*]] = load i16, ptr [[ARRAYIDX10_10]], align 2 359; CHECK-NEXT: [[CONV11_10:%.*]] = zext i16 [[TMP72]] to i32 360; CHECK-NEXT: br i1 [[CMP1_10]], label [[IF_THEN_10:%.*]], label [[IF_ELSE_10:%.*]] 361; CHECK: if.else.10: 362; CHECK-NEXT: [[ADD21_10:%.*]] = sub nsw i32 [[CONV5_10]], [[CONV_10]] 363; CHECK-NEXT: [[MUL25_10:%.*]] = mul i32 [[ADD21_10]], [[CONV11_10]] 364; CHECK-NEXT: [[SHR26_10:%.*]] = lshr i32 [[MUL25_10]], 16 365; CHECK-NEXT: [[TMP73:%.*]] = trunc nuw i32 [[SHR26_10]] to i16 366; CHECK-NEXT: [[CONV28_10:%.*]] = sub i16 0, [[TMP73]] 367; CHECK-NEXT: br label [[IF_END_10:%.*]] 368; CHECK: if.then.10: 369; CHECK-NEXT: [[ADD_10:%.*]] = add nuw nsw i32 [[CONV5_10]], [[CONV_10]] 370; CHECK-NEXT: [[MUL_10:%.*]] = mul i32 [[ADD_10]], [[CONV11_10]] 371; CHECK-NEXT: [[SHR_10:%.*]] = lshr i32 [[MUL_10]], 16 372; CHECK-NEXT: [[CONV12_10:%.*]] = trunc nuw i32 [[SHR_10]] to i16 373; CHECK-NEXT: br label [[IF_END_10]] 374; CHECK: if.end.10: 375; CHECK-NEXT: [[STOREMERGE_10:%.*]] = phi i16 [ [[CONV28_10]], [[IF_ELSE_10]] ], [ [[CONV12_10]], [[IF_THEN_10]] ] 376; CHECK-NEXT: store i16 [[STOREMERGE_10]], ptr [[ARRAYIDX_10]], align 2 377; CHECK-NEXT: [[OR_1046:%.*]] = or i16 [[OR_945]], [[STOREMERGE_10]] 378; CHECK-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 22 379; CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[ARRAYIDX_11]], align 2 380; CHECK-NEXT: [[CONV_11:%.*]] = sext i16 [[TMP74]] to i32 381; CHECK-NEXT: [[CMP1_11:%.*]] = icmp sgt i16 [[TMP74]], 0 382; CHECK-NEXT: [[ARRAYIDX4_11:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 22 383; CHECK-NEXT: [[TMP75:%.*]] = load i16, ptr [[ARRAYIDX4_11]], align 2 384; CHECK-NEXT: [[CONV5_11:%.*]] = zext i16 [[TMP75]] to i32 385; CHECK-NEXT: [[ARRAYIDX10_11:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 22 386; CHECK-NEXT: [[TMP76:%.*]] = load i16, ptr [[ARRAYIDX10_11]], align 2 387; CHECK-NEXT: [[CONV11_11:%.*]] = zext i16 [[TMP76]] to i32 388; CHECK-NEXT: br i1 [[CMP1_11]], label [[IF_THEN_11:%.*]], label [[IF_ELSE_11:%.*]] 389; CHECK: if.else.11: 390; CHECK-NEXT: [[ADD21_11:%.*]] = sub nsw i32 [[CONV5_11]], [[CONV_11]] 391; CHECK-NEXT: [[MUL25_11:%.*]] = mul i32 [[ADD21_11]], [[CONV11_11]] 392; CHECK-NEXT: [[SHR26_11:%.*]] = lshr i32 [[MUL25_11]], 16 393; CHECK-NEXT: [[TMP77:%.*]] = trunc nuw i32 [[SHR26_11]] to i16 394; CHECK-NEXT: [[CONV28_11:%.*]] = sub i16 0, [[TMP77]] 395; CHECK-NEXT: br label [[IF_END_11:%.*]] 396; CHECK: if.then.11: 397; CHECK-NEXT: [[ADD_11:%.*]] = add nuw nsw i32 [[CONV5_11]], [[CONV_11]] 398; CHECK-NEXT: [[MUL_11:%.*]] = mul i32 [[ADD_11]], [[CONV11_11]] 399; CHECK-NEXT: [[SHR_11:%.*]] = lshr i32 [[MUL_11]], 16 400; CHECK-NEXT: [[CONV12_11:%.*]] = trunc nuw i32 [[SHR_11]] to i16 401; CHECK-NEXT: br label [[IF_END_11]] 402; CHECK: if.end.11: 403; CHECK-NEXT: [[STOREMERGE_11:%.*]] = phi i16 [ [[CONV28_11]], [[IF_ELSE_11]] ], [ [[CONV12_11]], [[IF_THEN_11]] ] 404; CHECK-NEXT: store i16 [[STOREMERGE_11]], ptr [[ARRAYIDX_11]], align 2 405; CHECK-NEXT: [[OR_1147:%.*]] = or i16 [[OR_1046]], [[STOREMERGE_11]] 406; CHECK-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 24 407; CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[ARRAYIDX_12]], align 2 408; CHECK-NEXT: [[CONV_12:%.*]] = sext i16 [[TMP78]] to i32 409; CHECK-NEXT: [[CMP1_12:%.*]] = icmp sgt i16 [[TMP78]], 0 410; CHECK-NEXT: [[ARRAYIDX4_12:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 24 411; CHECK-NEXT: [[TMP79:%.*]] = load i16, ptr [[ARRAYIDX4_12]], align 2 412; CHECK-NEXT: [[CONV5_12:%.*]] = zext i16 [[TMP79]] to i32 413; CHECK-NEXT: [[ARRAYIDX10_12:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 24 414; CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[ARRAYIDX10_12]], align 2 415; CHECK-NEXT: [[CONV11_12:%.*]] = zext i16 [[TMP80]] to i32 416; CHECK-NEXT: br i1 [[CMP1_12]], label [[IF_THEN_12:%.*]], label [[IF_ELSE_12:%.*]] 417; CHECK: if.else.12: 418; CHECK-NEXT: [[ADD21_12:%.*]] = sub nsw i32 [[CONV5_12]], [[CONV_12]] 419; CHECK-NEXT: [[MUL25_12:%.*]] = mul i32 [[ADD21_12]], [[CONV11_12]] 420; CHECK-NEXT: [[SHR26_12:%.*]] = lshr i32 [[MUL25_12]], 16 421; CHECK-NEXT: [[TMP81:%.*]] = trunc nuw i32 [[SHR26_12]] to i16 422; CHECK-NEXT: [[CONV28_12:%.*]] = sub i16 0, [[TMP81]] 423; CHECK-NEXT: br label [[IF_END_12:%.*]] 424; CHECK: if.then.12: 425; CHECK-NEXT: [[ADD_12:%.*]] = add nuw nsw i32 [[CONV5_12]], [[CONV_12]] 426; CHECK-NEXT: [[MUL_12:%.*]] = mul i32 [[ADD_12]], [[CONV11_12]] 427; CHECK-NEXT: [[SHR_12:%.*]] = lshr i32 [[MUL_12]], 16 428; CHECK-NEXT: [[CONV12_12:%.*]] = trunc nuw i32 [[SHR_12]] to i16 429; CHECK-NEXT: br label [[IF_END_12]] 430; CHECK: if.end.12: 431; CHECK-NEXT: [[STOREMERGE_12:%.*]] = phi i16 [ [[CONV28_12]], [[IF_ELSE_12]] ], [ [[CONV12_12]], [[IF_THEN_12]] ] 432; CHECK-NEXT: store i16 [[STOREMERGE_12]], ptr [[ARRAYIDX_12]], align 2 433; CHECK-NEXT: [[OR_1248:%.*]] = or i16 [[OR_1147]], [[STOREMERGE_12]] 434; CHECK-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 26 435; CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[ARRAYIDX_13]], align 2 436; CHECK-NEXT: [[CONV_13:%.*]] = sext i16 [[TMP82]] to i32 437; CHECK-NEXT: [[CMP1_13:%.*]] = icmp sgt i16 [[TMP82]], 0 438; CHECK-NEXT: [[ARRAYIDX4_13:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 26 439; CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[ARRAYIDX4_13]], align 2 440; CHECK-NEXT: [[CONV5_13:%.*]] = zext i16 [[TMP83]] to i32 441; CHECK-NEXT: [[ARRAYIDX10_13:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 26 442; CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[ARRAYIDX10_13]], align 2 443; CHECK-NEXT: [[CONV11_13:%.*]] = zext i16 [[TMP84]] to i32 444; CHECK-NEXT: br i1 [[CMP1_13]], label [[IF_THEN_13:%.*]], label [[IF_ELSE_13:%.*]] 445; CHECK: if.else.13: 446; CHECK-NEXT: [[ADD21_13:%.*]] = sub nsw i32 [[CONV5_13]], [[CONV_13]] 447; CHECK-NEXT: [[MUL25_13:%.*]] = mul i32 [[ADD21_13]], [[CONV11_13]] 448; CHECK-NEXT: [[SHR26_13:%.*]] = lshr i32 [[MUL25_13]], 16 449; CHECK-NEXT: [[TMP85:%.*]] = trunc nuw i32 [[SHR26_13]] to i16 450; CHECK-NEXT: [[CONV28_13:%.*]] = sub i16 0, [[TMP85]] 451; CHECK-NEXT: br label [[IF_END_13:%.*]] 452; CHECK: if.then.13: 453; CHECK-NEXT: [[ADD_13:%.*]] = add nuw nsw i32 [[CONV5_13]], [[CONV_13]] 454; CHECK-NEXT: [[MUL_13:%.*]] = mul i32 [[ADD_13]], [[CONV11_13]] 455; CHECK-NEXT: [[SHR_13:%.*]] = lshr i32 [[MUL_13]], 16 456; CHECK-NEXT: [[CONV12_13:%.*]] = trunc nuw i32 [[SHR_13]] to i16 457; CHECK-NEXT: br label [[IF_END_13]] 458; CHECK: if.end.13: 459; CHECK-NEXT: [[STOREMERGE_13:%.*]] = phi i16 [ [[CONV28_13]], [[IF_ELSE_13]] ], [ [[CONV12_13]], [[IF_THEN_13]] ] 460; CHECK-NEXT: store i16 [[STOREMERGE_13]], ptr [[ARRAYIDX_13]], align 2 461; CHECK-NEXT: [[OR_1349:%.*]] = or i16 [[OR_1248]], [[STOREMERGE_13]] 462; CHECK-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 28 463; CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[ARRAYIDX_14]], align 2 464; CHECK-NEXT: [[CONV_14:%.*]] = sext i16 [[TMP86]] to i32 465; CHECK-NEXT: [[CMP1_14:%.*]] = icmp sgt i16 [[TMP86]], 0 466; CHECK-NEXT: [[ARRAYIDX4_14:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 28 467; CHECK-NEXT: [[TMP87:%.*]] = load i16, ptr [[ARRAYIDX4_14]], align 2 468; CHECK-NEXT: [[CONV5_14:%.*]] = zext i16 [[TMP87]] to i32 469; CHECK-NEXT: [[ARRAYIDX10_14:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 28 470; CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[ARRAYIDX10_14]], align 2 471; CHECK-NEXT: [[CONV11_14:%.*]] = zext i16 [[TMP88]] to i32 472; CHECK-NEXT: br i1 [[CMP1_14]], label [[IF_THEN_14:%.*]], label [[IF_ELSE_14:%.*]] 473; CHECK: if.else.14: 474; CHECK-NEXT: [[ADD21_14:%.*]] = sub nsw i32 [[CONV5_14]], [[CONV_14]] 475; CHECK-NEXT: [[MUL25_14:%.*]] = mul i32 [[ADD21_14]], [[CONV11_14]] 476; CHECK-NEXT: [[SHR26_14:%.*]] = lshr i32 [[MUL25_14]], 16 477; CHECK-NEXT: [[TMP89:%.*]] = trunc nuw i32 [[SHR26_14]] to i16 478; CHECK-NEXT: [[CONV28_14:%.*]] = sub i16 0, [[TMP89]] 479; CHECK-NEXT: br label [[IF_END_14:%.*]] 480; CHECK: if.then.14: 481; CHECK-NEXT: [[ADD_14:%.*]] = add nuw nsw i32 [[CONV5_14]], [[CONV_14]] 482; CHECK-NEXT: [[MUL_14:%.*]] = mul i32 [[ADD_14]], [[CONV11_14]] 483; CHECK-NEXT: [[SHR_14:%.*]] = lshr i32 [[MUL_14]], 16 484; CHECK-NEXT: [[CONV12_14:%.*]] = trunc nuw i32 [[SHR_14]] to i16 485; CHECK-NEXT: br label [[IF_END_14]] 486; CHECK: if.end.14: 487; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i16 [ [[CONV28_14]], [[IF_ELSE_14]] ], [ [[CONV12_14]], [[IF_THEN_14]] ] 488; CHECK-NEXT: store i16 [[STOREMERGE_14]], ptr [[ARRAYIDX_14]], align 2 489; CHECK-NEXT: [[OR_1450:%.*]] = or i16 [[OR_1349]], [[STOREMERGE_14]] 490; CHECK-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 30 491; CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[ARRAYIDX_15]], align 2 492; CHECK-NEXT: [[CONV_15:%.*]] = sext i16 [[TMP90]] to i32 493; CHECK-NEXT: [[CMP1_15:%.*]] = icmp sgt i16 [[TMP90]], 0 494; CHECK-NEXT: [[ARRAYIDX4_15:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 30 495; CHECK-NEXT: [[TMP91:%.*]] = load i16, ptr [[ARRAYIDX4_15]], align 2 496; CHECK-NEXT: [[CONV5_15:%.*]] = zext i16 [[TMP91]] to i32 497; CHECK-NEXT: [[ARRAYIDX10_15:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 30 498; CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[ARRAYIDX10_15]], align 2 499; CHECK-NEXT: [[CONV11_15:%.*]] = zext i16 [[TMP92]] to i32 500; CHECK-NEXT: br i1 [[CMP1_15]], label [[IF_THEN_15:%.*]], label [[IF_ELSE_15:%.*]] 501; CHECK: if.else.15: 502; CHECK-NEXT: [[ADD21_15:%.*]] = sub nsw i32 [[CONV5_15]], [[CONV_15]] 503; CHECK-NEXT: [[MUL25_15:%.*]] = mul i32 [[ADD21_15]], [[CONV11_15]] 504; CHECK-NEXT: [[SHR26_15:%.*]] = lshr i32 [[MUL25_15]], 16 505; CHECK-NEXT: [[TMP93:%.*]] = trunc nuw i32 [[SHR26_15]] to i16 506; CHECK-NEXT: [[CONV28_15:%.*]] = sub i16 0, [[TMP93]] 507; CHECK-NEXT: br label [[IF_END_15]] 508; CHECK: if.then.15: 509; CHECK-NEXT: [[ADD_15:%.*]] = add nuw nsw i32 [[CONV5_15]], [[CONV_15]] 510; CHECK-NEXT: [[MUL_15:%.*]] = mul i32 [[ADD_15]], [[CONV11_15]] 511; CHECK-NEXT: [[SHR_15:%.*]] = lshr i32 [[MUL_15]], 16 512; CHECK-NEXT: [[CONV12_15:%.*]] = trunc nuw i32 [[SHR_15]] to i16 513; CHECK-NEXT: br label [[IF_END_15]] 514; CHECK: if.end.15: 515; CHECK-NEXT: [[STOREMERGE_15:%.*]] = phi i16 [ [[CONV28_15]], [[IF_ELSE_15]] ], [ [[CONV12_15]], [[IF_THEN_15]] ] 516; CHECK-NEXT: store i16 [[STOREMERGE_15]], ptr [[ARRAYIDX_15]], align 2 517; CHECK-NEXT: [[OR_1551:%.*]] = or i16 [[OR_1450]], [[STOREMERGE_15]] 518; CHECK-NEXT: [[OR_15]] = sext i16 [[OR_1551]] to i32 519; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] 520; 521entry: 522 %dct.addr = alloca ptr, align 8 523 %mf.addr = alloca ptr, align 8 524 %bias.addr = alloca ptr, align 8 525 %nz = alloca i32, align 4 526 %i = alloca i32, align 4 527 store ptr %dct, ptr %dct.addr, align 8 528 store ptr %mf, ptr %mf.addr, align 8 529 store ptr %bias, ptr %bias.addr, align 8 530 call void @llvm.lifetime.start.p0(i64 4, ptr %nz) #2 531 store i32 0, ptr %nz, align 4 532 call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2 533 store i32 0, ptr %i, align 4 534 br label %for.cond 535 536for.cond: ; preds = %for.inc, %entry 537 %0 = load i32, ptr %i, align 4 538 %cmp = icmp slt i32 %0, 16 539 br i1 %cmp, label %for.body, label %for.cond.cleanup 540 541for.cond.cleanup: ; preds = %for.cond 542 call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2 543 br label %for.end 544 545for.body: ; preds = %for.cond 546 %1 = load ptr, ptr %dct.addr, align 8 547 %2 = load i32, ptr %i, align 4 548 %idxprom = sext i32 %2 to i64 549 %arrayidx = getelementptr inbounds i16, ptr %1, i64 %idxprom 550 %3 = load i16, ptr %arrayidx, align 2 551 %conv = sext i16 %3 to i32 552 %cmp1 = icmp sgt i32 %conv, 0 553 br i1 %cmp1, label %if.then, label %if.else 554 555if.then: ; preds = %for.body 556 %4 = load ptr, ptr %bias.addr, align 8 557 %5 = load i32, ptr %i, align 4 558 %idxprom3 = sext i32 %5 to i64 559 %arrayidx4 = getelementptr inbounds i16, ptr %4, i64 %idxprom3 560 %6 = load i16, ptr %arrayidx4, align 2 561 %conv5 = zext i16 %6 to i32 562 %7 = load ptr, ptr %dct.addr, align 8 563 %8 = load i32, ptr %i, align 4 564 %idxprom6 = sext i32 %8 to i64 565 %arrayidx7 = getelementptr inbounds i16, ptr %7, i64 %idxprom6 566 %9 = load i16, ptr %arrayidx7, align 2 567 %conv8 = sext i16 %9 to i32 568 %add = add i32 %conv5, %conv8 569 %10 = load ptr, ptr %mf.addr, align 8 570 %11 = load i32, ptr %i, align 4 571 %idxprom9 = sext i32 %11 to i64 572 %arrayidx10 = getelementptr inbounds i16, ptr %10, i64 %idxprom9 573 %12 = load i16, ptr %arrayidx10, align 2 574 %conv11 = zext i16 %12 to i32 575 %mul = mul i32 %add, %conv11 576 %shr = lshr i32 %mul, 16 577 %conv12 = trunc i32 %shr to i16 578 %13 = load ptr, ptr %dct.addr, align 8 579 %14 = load i32, ptr %i, align 4 580 %idxprom13 = sext i32 %14 to i64 581 %arrayidx14 = getelementptr inbounds i16, ptr %13, i64 %idxprom13 582 store i16 %conv12, ptr %arrayidx14, align 2 583 br label %if.end 584 585if.else: ; preds = %for.body 586 %15 = load ptr, ptr %bias.addr, align 8 587 %16 = load i32, ptr %i, align 4 588 %idxprom15 = sext i32 %16 to i64 589 %arrayidx16 = getelementptr inbounds i16, ptr %15, i64 %idxprom15 590 %17 = load i16, ptr %arrayidx16, align 2 591 %conv17 = zext i16 %17 to i32 592 %18 = load ptr, ptr %dct.addr, align 8 593 %19 = load i32, ptr %i, align 4 594 %idxprom18 = sext i32 %19 to i64 595 %arrayidx19 = getelementptr inbounds i16, ptr %18, i64 %idxprom18 596 %20 = load i16, ptr %arrayidx19, align 2 597 %conv20 = sext i16 %20 to i32 598 %sub = sub nsw i32 0, %conv20 599 %add21 = add i32 %conv17, %sub 600 %21 = load ptr, ptr %mf.addr, align 8 601 %22 = load i32, ptr %i, align 4 602 %idxprom22 = sext i32 %22 to i64 603 %arrayidx23 = getelementptr inbounds i16, ptr %21, i64 %idxprom22 604 %23 = load i16, ptr %arrayidx23, align 2 605 %conv24 = zext i16 %23 to i32 606 %mul25 = mul i32 %add21, %conv24 607 %shr26 = lshr i32 %mul25, 16 608 %sub27 = sub nsw i32 0, %shr26 609 %conv28 = trunc i32 %sub27 to i16 610 %24 = load ptr, ptr %dct.addr, align 8 611 %25 = load i32, ptr %i, align 4 612 %idxprom29 = sext i32 %25 to i64 613 %arrayidx30 = getelementptr inbounds i16, ptr %24, i64 %idxprom29 614 store i16 %conv28, ptr %arrayidx30, align 2 615 br label %if.end 616 617if.end: ; preds = %if.else, %if.then 618 %26 = load ptr, ptr %dct.addr, align 8 619 %27 = load i32, ptr %i, align 4 620 %idxprom31 = sext i32 %27 to i64 621 %arrayidx32 = getelementptr inbounds i16, ptr %26, i64 %idxprom31 622 %28 = load i16, ptr %arrayidx32, align 2 623 %conv33 = sext i16 %28 to i32 624 %29 = load i32, ptr %nz, align 4 625 %or = or i32 %29, %conv33 626 store i32 %or, ptr %nz, align 4 627 br label %for.inc 628 629for.inc: ; preds = %if.end 630 %30 = load i32, ptr %i, align 4 631 %inc = add nsw i32 %30, 1 632 store i32 %inc, ptr %i, align 4 633 br label %for.cond 634 635for.end: ; preds = %for.cond.cleanup 636 %31 = load i32, ptr %nz, align 4 637 %tobool = icmp ne i32 %31, 0 638 %lnot = xor i1 %tobool, true 639 %lnot34 = xor i1 %lnot, true 640 %lnot.ext = zext i1 %lnot34 to i32 641 call void @llvm.lifetime.end.p0(i64 4, ptr %nz) #2 642 ret i32 %lnot.ext 643} 644 645; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) 646declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 647 648; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) 649declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 650 651