1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -passes="default<O3>" -S -o - %s | FileCheck %s 3 4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 5target triple = "arm64-apple-macosx14.0.0" 6 7define void @s172(i32 noundef %xa, i32 noundef %xb, ptr noundef %a, ptr noundef %b) { 8; CHECK-LABEL: define void @s172( 9; CHECK-SAME: i32 noundef [[XA:%.*]], i32 noundef [[XB:%.*]], ptr noundef captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { 10; CHECK-NEXT: entry: 11; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[XA]], 32001 12; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] 13; CHECK: for.body.preheader: 14; CHECK-NEXT: [[SUB:%.*]] = add i32 [[XA]], -1 15; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[SUB]] to i64 16; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[XB]] to i64 17; CHECK-NEXT: [[TMP2:%.*]] = add nsw i64 [[TMP1]], [[TMP0]] 18; CHECK-NEXT: [[SMAX7:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP2]], i64 32000) 19; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 32000 20; CHECK-NEXT: [[UMIN8:%.*]] = zext i1 [[TMP3]] to i64 21; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[TMP2]], [[UMIN8]] 22; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[SMAX7]], [[TMP4]] 23; CHECK-NEXT: [[UMAX9:%.*]] = tail call i64 @llvm.umax.i64(i64 [[TMP1]], i64 1) 24; CHECK-NEXT: [[TMP6:%.*]] = udiv i64 [[TMP5]], [[UMAX9]] 25; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], [[UMIN8]] 26; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 1 27; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ugt i64 [[TMP8]], 23 28; CHECK-NEXT: [[IDENT_CHECK_NOT:%.*]] = icmp eq i32 [[XB]], 1 29; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[MIN_ITERS_CHECK]], [[IDENT_CHECK_NOT]] 30; CHECK-NEXT: br i1 [[OR_COND]], label [[VECTOR_MEMCHECK:%.*]], label [[FOR_BODY_PREHEADER13:%.*]] 31; CHECK: vector.memcheck: 32; CHECK-NEXT: [[TMP9:%.*]] = shl nsw i64 [[TMP0]], 2 33; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP9]] 34; CHECK-NEXT: [[TMP10:%.*]] = add nsw i64 [[TMP1]], [[TMP0]] 35; CHECK-NEXT: [[SMAX:%.*]] = tail call i64 @llvm.smax.i64(i64 [[TMP10]], i64 32000) 36; CHECK-NEXT: [[TMP11:%.*]] = icmp slt i64 [[TMP10]], 32000 37; CHECK-NEXT: [[UMIN:%.*]] = zext i1 [[TMP11]] to i64 38; CHECK-NEXT: [[TMP12:%.*]] = add nsw i64 [[TMP10]], [[UMIN]] 39; CHECK-NEXT: [[TMP13:%.*]] = sub i64 [[SMAX]], [[TMP12]] 40; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP13]], [[UMIN]] 41; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], [[TMP0]] 42; CHECK-NEXT: [[TMP16:%.*]] = shl i64 [[TMP15]], 2 43; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 4 44; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP17]] 45; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP9]] 46; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP17]] 47; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP6]] 48; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP5]], [[SCEVGEP4]] 49; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 50; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[FOR_BODY_PREHEADER13]], label [[VECTOR_PH:%.*]] 51; CHECK: vector.ph: 52; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP8]], -8 53; CHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[N_VEC]], [[TMP1]] 54; CHECK-NEXT: [[IND_END:%.*]] = add i64 [[TMP18]], [[TMP0]] 55; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 56; CHECK: vector.body: 57; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 58; CHECK-NEXT: [[TMP19:%.*]] = mul nuw i64 [[INDEX]], [[TMP1]] 59; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[TMP19]], [[TMP0]] 60; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[OFFSET_IDX]] 61; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP20]], i64 16 62; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP20]], align 4, !alias.scope [[META0:![0-9]+]] 63; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP21]], align 4, !alias.scope [[META0]] 64; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[OFFSET_IDX]] 65; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP22]], i64 16 66; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope [[META3:![0-9]+]], !noalias [[META0]] 67; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4, !alias.scope [[META3]], !noalias [[META0]] 68; CHECK-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD11]], [[WIDE_LOAD]] 69; CHECK-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD12]], [[WIDE_LOAD10]] 70; CHECK-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP22]], align 4, !alias.scope [[META3]], !noalias [[META0]] 71; CHECK-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP23]], align 4, !alias.scope [[META3]], !noalias [[META0]] 72; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 73; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 74; CHECK-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 75; CHECK: middle.block: 76; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP8]], [[N_VEC]] 77; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY_PREHEADER13]] 78; CHECK: for.body.preheader13: 79; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ [[TMP0]], [[FOR_BODY_PREHEADER]] ], [ [[TMP0]], [[VECTOR_MEMCHECK]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ] 80; CHECK-NEXT: br label [[FOR_BODY:%.*]] 81; CHECK: for.body: 82; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PREHEADER13]] ] 83; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] 84; CHECK-NEXT: [[L_B:%.*]] = load i32, ptr [[GEP_B]], align 4 85; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]] 86; CHECK-NEXT: [[L_A:%.*]] = load i32, ptr [[GEP_A]], align 4 87; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[L_A]], [[L_B]] 88; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_A]], align 4 89; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP1]] 90; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], 32000 91; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP9:![0-9]+]] 92; CHECK: for.end: 93; CHECK-NEXT: ret void 94; 95entry: 96 %sub = sub nsw i32 %xa, 1 97 br label %for.cond 98 99for.cond: 100 %i.0 = phi i32 [ %sub, %entry ], [ %add3, %for.inc ] 101 %cmp = icmp slt i32 %i.0, 32000 102 br i1 %cmp, label %for.body, label %for.cond.cleanup 103 104for.body: 105 %idxprom = sext i32 %i.0 to i64 106 %gep.b = getelementptr inbounds i32, ptr %b, i64 %idxprom 107 %l.b = load i32, ptr %gep.b, align 4 108 %idxprom1 = sext i32 %i.0 to i64 109 %gep.a = getelementptr inbounds i32, ptr %a, i64 %idxprom1 110 %l.a = load i32, ptr %gep.a , align 4 111 %add = add nsw i32 %l.a, %l.b 112 store i32 %add, ptr %gep.a, align 4 113 br label %for.inc 114 115for.inc: 116 %add3 = add nsw i32 %i.0, %xb 117 br label %for.cond, !llvm.loop !0 118 119for.cond.cleanup: 120 br label %for.end 121 122for.end: 123 ret void 124} 125 126!0 = distinct !{!0, !1} 127!1 = !{!"llvm.loop.mustprogress"} 128;. 129; CHECK: [[META0]] = !{[[META1:![0-9]+]]} 130; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]} 131; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"} 132; CHECK: [[META3]] = !{[[META4:![0-9]+]]} 133; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]} 134; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]], [[META8:![0-9]+]]} 135; CHECK: [[META6]] = !{!"llvm.loop.mustprogress"} 136; CHECK: [[META7]] = !{!"llvm.loop.isvectorized", i32 1} 137; CHECK: [[META8]] = !{!"llvm.loop.unroll.runtime.disable"} 138; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META6]], [[META7]]} 139;. 140