1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=newgvn < %s | FileCheck %s 3 4; Check that we do not use keywords only available for some members of a 5; congruence class when simplifying. 6 7target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 8target triple = "x86_64-unknown-linux-gnu" 9 10@f = external global i64, align 8 11@b = external global i1, align 8 12 13define i64 @ashr_lsh_nsw(i64 %tmp) { 14; CHECK-LABEL: @ashr_lsh_nsw( 15; CHECK-NEXT: entry: 16; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32 17; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8 18; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32 19; CHECK-NEXT: ret i64 [[CONV7]] 20; 21entry: ; preds = %if.then 22 %conv3 = shl nsw i64 %tmp, 32 23 store i64 %conv3, ptr @f, align 8 24 %sext = shl i64 %tmp, 32 25 %conv7 = ashr exact i64 %sext, 32 26 ret i64 %conv7 27} 28 29define i64 @ashr_lsh_nuw(i64 %tmp) { 30; CHECK-LABEL: @ashr_lsh_nuw( 31; CHECK-NEXT: entry: 32; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32 33; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8 34; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32 35; CHECK-NEXT: ret i64 [[CONV7]] 36; 37entry: ; preds = %if.then 38 %conv3 = shl nuw i64 %tmp, 32 39 store i64 %conv3, ptr @f, align 8 40 %sext = shl i64 %tmp, 32 41 %conv7 = ashr exact i64 %sext, 32 42 ret i64 %conv7 43} 44 45define i64 @lshr_lsh_nuw(i64 %tmp) { 46; CHECK-LABEL: @lshr_lsh_nuw( 47; CHECK-NEXT: entry: 48; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32 49; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8 50; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[CONV3]], 32 51; CHECK-NEXT: ret i64 [[LSHR]] 52; 53entry: 54 %conv3 = shl nuw i64 %tmp, 32 55 store i64 %conv3, ptr @f, align 8 56 %sext = shl i64 %tmp, 32 57 %lshr = lshr i64 %sext, 32 58 ret i64 %lshr 59} 60 61define i32 @udiv_exact_mul(i32 %x, i32 %y, i1 %arg2) { 62; CHECK-LABEL: @udiv_exact_mul( 63; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB2:%.*]], label [[BB1:%.*]] 64; CHECK: bb1: 65; CHECK-NEXT: [[S1:%.*]] = udiv exact i32 [[X:%.*]], [[Y:%.*]] 66; CHECK-NEXT: [[S2:%.*]] = mul i32 [[S1]], [[Y]] 67; CHECK-NEXT: ret i32 [[S2]] 68; CHECK: bb2: 69; CHECK-NEXT: [[S1_2:%.*]] = udiv i32 [[X]], [[Y]] 70; CHECK-NEXT: [[S2_2:%.*]] = mul i32 [[S1_2]], [[Y]] 71; CHECK-NEXT: ret i32 [[S2_2]] 72; 73 br i1 %arg2, label %bb2, label %bb1 74bb1: 75 %s1 = udiv exact i32 %x, %y 76 %s2 = mul i32 %s1, %y 77 ret i32 %s2 78 79bb2: 80 %s1.2 = udiv i32 %x, %y 81 %s2.2 = mul i32 %s1.2, %y 82 ret i32 %s2.2 83} 84 85define i1 @add_nuw_icmp(i32 %x, i32 %y, i1 %arg2) { 86; CHECK-LABEL: @add_nuw_icmp( 87; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] 88; CHECK: bb1: 89; CHECK-NEXT: [[Z:%.*]] = add i32 [[Y:%.*]], 1 90; CHECK-NEXT: [[S1:%.*]] = add i32 [[X:%.*]], [[Z]] 91; CHECK-NEXT: [[S2:%.*]] = add i32 [[X]], [[Y]] 92; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[S1]], [[S2]] 93; CHECK-NEXT: ret i1 [[C]] 94; CHECK: bb2: 95; CHECK-NEXT: [[Z_2:%.*]] = add nuw i32 [[Y]], 1 96; CHECK-NEXT: [[S1_2:%.*]] = add nuw i32 [[X]], [[Z_2]] 97; CHECK-NEXT: [[S2_2:%.*]] = add nuw i32 [[X]], [[Y]] 98; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i32 [[S1_2]], [[S2_2]] 99; CHECK-NEXT: ret i1 [[C_2]] 100; 101 br i1 %arg2, label %bb1, label %bb2 102 103bb1: 104 %z = add i32 %y, 1 105 %s1 = add i32 %x, %z 106 %s2 = add i32 %x, %y 107 %c = icmp ugt i32 %s1, %s2 108 ret i1 %c 109 110bb2: 111 %z.2 = add nuw i32 %y, 1 112 %s1.2 = add nuw i32 %x, %z.2 113 %s2.2 = add nuw i32 %x, %y 114 %c.2 = icmp ugt i32 %s1.2, %s2.2 115 ret i1 %c.2 116} 117