1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S %s | FileCheck %s 3target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32" 4 5define void @tail_fold_switch(ptr %dst, i32 %0) { 6; CHECK-LABEL: define void @tail_fold_switch( 7; CHECK-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) { 8; CHECK-NEXT: [[ENTRY:.*]]: 9; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 10; CHECK: [[VECTOR_PH]]: 11; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0 12; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 13; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], splat (i32 1) 14; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 15; CHECK: [[VECTOR_BODY]]: 16; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ] 17; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ] 18; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[VEC_IND]], splat (i64 4) 19; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP2]], <4 x i1> zeroinitializer 20; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i32 0 21; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] 22; CHECK: [[PRED_STORE_IF]]: 23; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0 24; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP5]] 25; CHECK-NEXT: store i32 0, ptr [[TMP6]], align 4 26; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]] 27; CHECK: [[PRED_STORE_CONTINUE]]: 28; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP3]], i32 1 29; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]] 30; CHECK: [[PRED_STORE_IF1]]: 31; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 32; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP8]] 33; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 4 34; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]] 35; CHECK: [[PRED_STORE_CONTINUE2]]: 36; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP3]], i32 2 37; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]] 38; CHECK: [[PRED_STORE_IF3]]: 39; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 2 40; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP11]] 41; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 4 42; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]] 43; CHECK: [[PRED_STORE_CONTINUE4]]: 44; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP3]], i32 3 45; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]] 46; CHECK: [[PRED_STORE_IF5]]: 47; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 3 48; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP14]] 49; CHECK-NEXT: store i32 0, ptr [[TMP15]], align 4 50; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]] 51; CHECK: [[PRED_STORE_CONTINUE6]]: 52; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 53; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 54; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8 55; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 56; CHECK: [[MIDDLE_BLOCK]]: 57; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]] 58; CHECK: [[SCALAR_PH]]: 59; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 8, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 60; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 61; CHECK: [[LOOP_HEADER]]: 62; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 63; CHECK-NEXT: switch i32 [[TMP0]], label %[[LOOP_LATCH]] [ 64; CHECK-NEXT: i32 0, label %[[LOOP_LATCH]] 65; CHECK-NEXT: i32 1, label %[[IF_THEN:.*]] 66; CHECK-NEXT: ] 67; CHECK: [[IF_THEN]]: 68; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] 69; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4 70; CHECK-NEXT: br label %[[LOOP_LATCH]] 71; CHECK: [[LOOP_LATCH]]: 72; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 73; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 4 74; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] 75; CHECK: [[EXIT]]: 76; CHECK-NEXT: ret void 77; 78entry: 79 br label %loop.header 80 81loop.header: 82 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 83 switch i32 %0, label %loop.latch [ 84 i32 0, label %loop.latch 85 i32 1, label %if.then 86 ] 87 88if.then: 89 %gep = getelementptr inbounds i32, ptr %dst, i64 %iv 90 store i32 0, ptr %gep, align 4 91 br label %loop.latch 92 93loop.latch: 94 %iv.next = add i64 %iv, 1 95 %ec = icmp eq i64 %iv, 4 96 br i1 %ec, label %exit, label %loop.header 97 98exit: 99 ret void 100} 101;. 102; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 103; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 104; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 105; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 106;. 107