1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -passes='loop(loop-deletion),loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s 3 4; Note: loop-deletion is needed to populate SCEV block dispositions. 5 6target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 7 8define void @test_pr63368(i1 %c, ptr %A) { 9; CHECK-LABEL: define void @test_pr63368 10; CHECK-SAME: (i1 [[C:%.*]], ptr [[A:%.*]]) { 11; CHECK-NEXT: entry: 12; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 13; CHECK: vector.ph: 14; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 15; CHECK: vector.body: 16; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 17; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 18; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 19; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100 20; CHECK-NEXT: br i1 [[TMP1]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 21; CHECK: middle.block: 22; CHECK-NEXT: br i1 true, label [[EXIT_1:%.*]], label [[SCALAR_PH]] 23; CHECK: scalar.ph: 24; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 25; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]] 26; CHECK: loop.1.header: 27; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_1_LATCH:%.*]] ] 28; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[A]], align 4 29; CHECK-NEXT: br i1 [[C]], label [[LOOP_1_LATCH]], label [[LOOP_1_LATCH]] 30; CHECK: loop.1.latch: 31; CHECK-NEXT: [[L_LCSSA:%.*]] = phi i32 [ [[L]], [[LOOP_1_HEADER]] ], [ [[L]], [[LOOP_1_HEADER]] ] 32; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i32 [[IV_1]], 1 33; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i32 [[IV_1_NEXT]], 100 34; CHECK-NEXT: br i1 [[EC_1]], label [[EXIT_1]], label [[LOOP_1_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] 35; CHECK: exit.1: 36; CHECK-NEXT: [[L_LCSSA_LCSSA:%.*]] = phi i32 [ [[L_LCSSA]], [[LOOP_1_LATCH]] ], [ [[TMP0]], [[MIDDLE_BLOCK]] ] 37; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[L_LCSSA_LCSSA]], i32 -1) 38; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[SMAX1]], 2 39; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4 40; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH3:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 41; CHECK: vector.scevcheck: 42; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[L_LCSSA_LCSSA]], i32 -1) 43; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SMAX]], 1 44; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8 45; CHECK-NEXT: [[TMP5:%.*]] = add i8 1, [[TMP4]] 46; CHECK-NEXT: [[TMP6:%.*]] = icmp slt i8 [[TMP5]], 1 47; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP3]], 255 48; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]] 49; CHECK-NEXT: br i1 [[TMP8]], label [[SCALAR_PH3]], label [[VECTOR_PH4:%.*]] 50; CHECK: vector.ph4: 51; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 4 52; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[N_MOD_VF]] 53; CHECK-NEXT: [[IND_END:%.*]] = trunc i32 [[N_VEC]] to i8 54; CHECK-NEXT: br label [[VECTOR_BODY5:%.*]] 55; CHECK: vector.body5: 56; CHECK-NEXT: [[INDEX8:%.*]] = phi i32 [ 0, [[VECTOR_PH4]] ], [ [[INDEX_NEXT9:%.*]], [[VECTOR_BODY5]] ] 57; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX8]] to i8 58; CHECK-NEXT: [[TMP14:%.*]] = add i8 [[OFFSET_IDX]], 0 59; CHECK-NEXT: [[TMP15:%.*]] = add i8 [[TMP14]], 1 60; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[A]], i8 [[TMP15]] 61; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP16]], i32 0 62; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP17]], align 1 63; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i32 [[INDEX8]], 4 64; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT9]], [[N_VEC]] 65; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK2:%.*]], label [[VECTOR_BODY5]], !llvm.loop [[LOOP4:![0-9]+]] 66; CHECK: middle.block2: 67; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]] 68; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT_2:%.*]], label [[SCALAR_PH3]] 69; CHECK: scalar.ph3: 70; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK2]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[EXIT_1]] ] 71; CHECK-NEXT: br label [[LOOP_2:%.*]] 72; CHECK: loop.2: 73; CHECK-NEXT: [[IV_2:%.*]] = phi i8 [ [[BC_RESUME_VAL8]], [[SCALAR_PH3]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_2]] ] 74; CHECK-NEXT: [[IV_2_NEXT]] = add i8 [[IV_2]], 1 75; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i8, ptr [[A]], i8 [[IV_2_NEXT]] 76; CHECK-NEXT: store i8 0, ptr [[GEP_A]], align 1 77; CHECK-NEXT: [[IV_2_SEXT:%.*]] = sext i8 [[IV_2]] to i32 78; CHECK-NEXT: [[EC_2:%.*]] = icmp sge i32 [[L_LCSSA_LCSSA]], [[IV_2_SEXT]] 79; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP_2]], label [[EXIT_2]], !llvm.loop [[LOOP5:![0-9]+]] 80; CHECK: exit.2: 81; CHECK-NEXT: ret void 82; 83 84entry: 85 br label %loop.1.header 86 87loop.1.header: 88 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ] 89 %l = load i32, ptr %A 90 br i1 %c, label %loop.1.latch, label %loop.1.latch 91 92loop.1.latch: 93 %l.lcssa = phi i32 [ %l, %loop.1.header ], [ %l, %loop.1.header ] 94 %iv.1.next = add nuw nsw i32 %iv.1, 1 95 %ec.1 = icmp eq i32 %iv.1.next, 100 96 br i1 %ec.1, label %exit.1, label %loop.1.header 97 98exit.1: 99 %l.lcssa.lcssa = phi i32 [ %l.lcssa, %loop.1.latch ] 100 br label %loop.2 101 102loop.2: 103 %iv.2 = phi i8 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ] 104 %iv.2.next = add i8 %iv.2, 1 105 %gep.A = getelementptr i8, ptr %A, i8 %iv.2.next 106 store i8 0, ptr %gep.A 107 %iv.2.sext = sext i8 %iv.2 to i32 108 %ec.2 = icmp sge i32 %l.lcssa.lcssa, %iv.2.sext 109 br i1 %ec.2, label %loop.2, label %exit.2 110 111exit.2: 112 ret void 113} 114