1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -scalable-vectorization=on -force-target-supports-scalable-vectors=true -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck %s 3 4define i32 @iv_live_out_wide(ptr %dst) { 5; CHECK-LABEL: define i32 @iv_live_out_wide( 6; CHECK-SAME: ptr [[DST:%.*]]) { 7; CHECK-NEXT: [[ENTRY:.*]]: 8; CHECK-NEXT: [[STEP_1:%.*]] = sext i8 0 to i32 9; CHECK-NEXT: [[STEP_2:%.*]] = add nsw i32 [[STEP_1]], 1 10; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32() 11; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], 4 12; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 2000, [[TMP1]] 13; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 14; CHECK: [[VECTOR_PH]]: 15; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32() 16; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], 4 17; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 2000, [[TMP3]] 18; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 2000, [[N_MOD_VF]] 19; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vscale.i32() 20; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 2 21; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 2 22; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32() 23; CHECK-NEXT: [[TMP8:%.*]] = mul <vscale x 2 x i32> [[TMP7]], splat (i32 1) 24; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i32> zeroinitializer, [[TMP8]] 25; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[TMP5]], i64 0 26; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 27; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[STEP_2]], i64 0 28; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 29; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 30; CHECK: [[VECTOR_BODY]]: 31; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 32; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 33; CHECK-NEXT: [[STEP_ADD:%.*]] = add <vscale x 2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] 34; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 0 35; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[TMP9]] 36; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i32 0 37; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64() 38; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 2 39; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[TMP13]] 40; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP11]], align 2 41; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP14]], align 2 42; CHECK-NEXT: [[TMP15:%.*]] = add <vscale x 2 x i32> [[BROADCAST_SPLAT2]], [[STEP_ADD]] 43; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP6]] 44; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i32> [[STEP_ADD]], [[BROADCAST_SPLAT]] 45; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 46; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 47; CHECK: [[MIDDLE_BLOCK]]: 48; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32() 49; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], 2 50; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP18]], 1 51; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 2 x i32> [[TMP15]], i32 [[TMP19]] 52; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 2000, [[N_VEC]] 53; CHECK-NEXT: br i1 [[CMP_N]], label %[[E_EXIT:.*]], label %[[SCALAR_PH]] 54; CHECK: [[SCALAR_PH]]: 55; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 56; CHECK-NEXT: br label %[[LOOP:.*]] 57; CHECK: [[LOOP]]: 58; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] 59; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[IV]] 60; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2 61; CHECK-NEXT: [[IV_NEXT]] = add i32 [[STEP_2]], [[IV]] 62; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[IV_NEXT]], 2000 63; CHECK-NEXT: br i1 [[CMP_I]], label %[[LOOP]], label %[[E_EXIT]], !llvm.loop [[LOOP3:![0-9]+]] 64; CHECK: [[E_EXIT]]: 65; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ] 66; CHECK-NEXT: ret i32 [[RES]] 67; 68entry: 69 %step.1 = sext i8 0 to i32 70 %step.2 = add nsw i32 %step.1, 1 71 br label %loop 72 73loop: 74 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 75 %gep.dst = getelementptr inbounds i16, ptr %dst, i32 %iv 76 store i16 0, ptr %gep.dst, align 2 77 %iv.next = add i32 %step.2, %iv 78 %cmp.i = icmp slt i32 %iv.next, 2000 79 br i1 %cmp.i, label %loop, label %e.exit 80 81e.exit: 82 %res = phi i32 [ %iv.next, %loop ] 83 ret i32 %res 84} 85;. 86; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 87; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 88; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 89; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 90;. 91