1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s 3 4define void @test1_pr58811() { 5; CHECK-LABEL: @test1_pr58811( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: br label [[LOOP_1_PREHEADER:%.*]] 8; CHECK: loop.1.preheader: 9; CHECK-NEXT: [[IV_1_PH:%.*]] = phi i32 [ [[SUB93_2:%.*]], [[UNREACHABLE_BB:%.*]] ], [ 0, [[ENTRY:%.*]] ] 10; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[IV_1_PH]] 11; CHECK-NEXT: br label [[LOOP_1:%.*]] 12; CHECK: loop.1: 13; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], [[LOOP_1]] ], [ [[TMP0]], [[LOOP_1_PREHEADER]] ] 14; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[IV_1_NEXT:%.*]], [[LOOP_1]] ], [ [[IV_1_PH]], [[LOOP_1_PREHEADER]] ] 15; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], [[LOOP_1]] ], [ 0, [[LOOP_1_PREHEADER]] ] 16; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_2]], -1 17; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 18; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_2]], [[IV_1]] 19; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]] 20; CHECK-NEXT: br i1 false, label [[LOOP_1]], label [[LOOP_2_PREHEADER:%.*]] 21; CHECK: loop.2.preheader: 22; CHECK-NEXT: [[INDUCTION_IV_LCSSA:%.*]] = phi i32 [ [[INDUCTION_IV]], [[LOOP_1]] ] 23; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], [[LOOP_1]] ] 24; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 25; CHECK: vector.ph: 26; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[INDUCTION_IV_LCSSA]] 27; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 28; CHECK: vector.body: 29; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 30; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 31; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196 32; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 33; CHECK: middle.block: 34; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i32 [[IND_END]], [[INDUCTION_IV_LCSSA]] 35; CHECK-NEXT: br i1 false, label [[LOOP_3_PREHEADER:%.*]], label [[SCALAR_PH]] 36; CHECK: scalar.ph: 37; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 196, [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_2_PREHEADER]] ] 38; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_2_PREHEADER]] ] 39; CHECK-NEXT: br label [[LOOP_2:%.*]] 40; CHECK: loop.2: 41; CHECK-NEXT: [[IV_3:%.*]] = phi i16 [ [[IV_3_NEXT:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 42; CHECK-NEXT: [[IV_4:%.*]] = phi i32 [ [[IV_4_NEXT:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 43; CHECK-NEXT: [[IV_4_NEXT]] = sub i32 [[IV_4]], [[IV_1_LCSSA]] 44; CHECK-NEXT: [[IV_3_NEXT]] = add i16 [[IV_3]], 1 45; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 198 46; CHECK-NEXT: br i1 [[CMP88_1]], label [[LOOP_2]], label [[LOOP_3_PREHEADER]], !llvm.loop [[LOOP3:![0-9]+]] 47; CHECK: loop.3.preheader: 48; CHECK-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], [[LOOP_2]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] 49; CHECK-NEXT: br label [[LOOP_3:%.*]] 50; CHECK: loop.3: 51; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], [[LOOP_3]] ], [ 0, [[LOOP_3_PREHEADER]] ] 52; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]] 53; CHECK-NEXT: br label [[LOOP_3]] 54; CHECK: unreachable.bb: 55; CHECK-NEXT: br label [[LOOP_1_PREHEADER]] 56; 57entry: 58 br label %loop.1.preheader 59 60loop.1.preheader: 61 %iv.1.ph = phi i32 [ %sub93.2, %unreachable.bb ], [ 0, %entry ] 62 br label %loop.1 63 64loop.1: 65 %iv.1 = phi i32 [ %iv.1.next, %loop.1 ], [ %iv.1.ph, %loop.1.preheader ] 66 %iv.2 = phi i32 [ %iv.2.next, %loop.1 ], [ 0, %loop.1.preheader ] 67 %iv.2.next = add i32 %iv.2, 1 68 %iv.1.next = add i32 %iv.2, %iv.1 69 br i1 false, label %loop.1, label %loop.2.preheader 70 71loop.2.preheader: 72 %iv.1.lcssa = phi i32 [ %iv.1, %loop.1 ] 73 br label %loop.2 74 75loop.2: 76 %iv.3 = phi i16 [ %iv.3.next, %loop.2 ], [ 0, %loop.2.preheader ] 77 %iv.4 = phi i32 [ %iv.4.next, %loop.2 ], [ 0, %loop.2.preheader ] 78 %iv.4.next = sub i32 %iv.4, %iv.1.lcssa 79 %iv.3.next = add i16 %iv.3, 1 80 %cmp88.1 = icmp ult i16 %iv.3, 198 81 br i1 %cmp88.1, label %loop.2, label %loop.3.preheader 82 83loop.3.preheader: 84 %iv.4.lcssa = phi i32 [ %iv.4, %loop.2 ] 85 br label %loop.3 86 87loop.3: 88 %iv.5 = phi i32 [ %sub93.2, %loop.3 ], [ 0, %loop.3.preheader ] 89 %sub93.2 = sub i32 %iv.5, %iv.4.lcssa 90 br label %loop.3 91 92unreachable.bb: ; No predecessors! 93 br label %loop.1.preheader 94} 95 96define void @test2_pr58811() { 97; CHECK-LABEL: @test2_pr58811( 98; CHECK-NEXT: entry: 99; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]] 100; CHECK: loop.1.header.loopexit: 101; CHECK-NEXT: [[SUB93_2_LCSSA:%.*]] = phi i32 [ [[SUB93_2:%.*]], [[LOOP_4:%.*]] ] 102; CHECK-NEXT: br label [[LOOP_1_HEADER]] 103; CHECK: loop.1.header: 104; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SUB93_2_LCSSA]], [[LOOP_1_HEADER_LOOPEXIT:%.*]] ] 105; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[P_1]], -1 106; CHECK-NEXT: br label [[LOOP_2:%.*]] 107; CHECK: loop.2: 108; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], [[LOOP_2]] ], [ [[TMP0]], [[LOOP_1_HEADER]] ] 109; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[P_1]], [[LOOP_1_HEADER]] ], [ [[ADD101:%.*]], [[LOOP_2]] ] 110; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ 0, [[LOOP_1_HEADER]] ], [ [[SUB93:%.*]], [[LOOP_2]] ] 111; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_3]], -1 112; CHECK-NEXT: [[SUB93]] = add i32 [[IV_3]], 1 113; CHECK-NEXT: [[ADD101]] = add i32 [[IV_3]], [[IV_2]] 114; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]] 115; CHECK-NEXT: br i1 false, label [[LOOP_2]], label [[LOOP_3_PREHEADER:%.*]] 116; CHECK: loop.3.preheader: 117; CHECK-NEXT: [[IV_2_LCSSA:%.*]] = phi i32 [ [[IV_2]], [[LOOP_2]] ] 118; CHECK-NEXT: [[INDUCTION_IV_LCSSA:%.*]] = phi i32 [ [[INDUCTION_IV]], [[LOOP_2]] ] 119; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 120; CHECK: vector.ph: 121; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[INDUCTION_IV_LCSSA]] 122; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 123; CHECK: vector.body: 124; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 125; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 126; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196 127; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 128; CHECK: middle.block: 129; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i32 [[IND_END]], [[INDUCTION_IV_LCSSA]] 130; CHECK-NEXT: br i1 false, label [[LOOP_4_PREHEADER:%.*]], label [[SCALAR_PH]] 131; CHECK: scalar.ph: 132; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 196, [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_3_PREHEADER]] ] 133; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_3_PREHEADER]] ] 134; CHECK-NEXT: br label [[LOOP_3:%.*]] 135; CHECK: loop.3: 136; CHECK-NEXT: [[IV_4:%.*]] = phi i16 [ [[INC_1:%.*]], [[LOOP_3]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 137; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_1:%.*]], [[LOOP_3]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 138; CHECK-NEXT: [[SUB93_1]] = sub i32 [[IV_5]], [[IV_2_LCSSA]] 139; CHECK-NEXT: [[INC_1]] = add i16 [[IV_4]], 1 140; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_4]], 198 141; CHECK-NEXT: br i1 [[CMP88_1]], label [[LOOP_3]], label [[LOOP_4_PREHEADER]], !llvm.loop [[LOOP5:![0-9]+]] 142; CHECK: loop.4.preheader: 143; CHECK-NEXT: [[IV_5_LCSSA:%.*]] = phi i32 [ [[IV_5]], [[LOOP_3]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] 144; CHECK-NEXT: br label [[LOOP_4]] 145; CHECK: loop.4: 146; CHECK-NEXT: [[IV_6:%.*]] = phi i32 [ [[SUB93_2]], [[LOOP_4]] ], [ 0, [[LOOP_4_PREHEADER]] ] 147; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_6]], [[IV_5_LCSSA]] 148; CHECK-NEXT: br i1 false, label [[LOOP_4]], label [[LOOP_1_HEADER_LOOPEXIT]] 149; 150entry: 151 br label %loop.1.header 152 153loop.1.header: 154 %p.1 = phi i32 [ 0, %entry ], [ %sub93.2, %loop.4 ] 155 br label %loop.2 156 157loop.2: 158 %iv.2 = phi i32 [ %p.1, %loop.1.header ], [ %add101, %loop.2 ] 159 %iv.3 = phi i32 [ 0, %loop.1.header ], [ %sub93, %loop.2 ] 160 %sub93 = add i32 %iv.3, 1 161 %add101 = add i32 %iv.3, %iv.2 162 br i1 false, label %loop.2, label %loop.3 163 164loop.3: 165 %iv.4 = phi i16 [ 0, %loop.2 ], [ %inc.1, %loop.3 ] 166 %iv.5 = phi i32 [ 0, %loop.2 ], [ %sub93.1, %loop.3 ] 167 %sub93.1 = sub i32 %iv.5, %iv.2 168 %inc.1 = add i16 %iv.4, 1 169 %cmp88.1 = icmp ult i16 %iv.4, 198 170 br i1 %cmp88.1, label %loop.3, label %loop.4 171 172loop.4: 173 %iv.6 = phi i32 [ 0, %loop.3 ], [ %sub93.2, %loop.4 ] 174 %sub93.2 = sub i32 %iv.6, %iv.5 175 br i1 false, label %loop.4, label %loop.1.header 176} 177 178define void @test3_pr58811() { 179; CHECK-LABEL: @test3_pr58811( 180; CHECK-NEXT: entry: 181; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]] 182; CHECK: loop.1.header: 183; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SUB93_2:%.*]], [[LOOP_1_LATCH:%.*]] ] 184; CHECK-NEXT: [[REM85:%.*]] = urem i32 1, [[P_1]] 185; CHECK-NEXT: br label [[LOOP_2:%.*]] 186; CHECK: loop.2: 187; CHECK-NEXT: [[P_2:%.*]] = phi i32 [ 1, [[LOOP_1_HEADER]] ], [ 0, [[LOOP_2]] ] 188; CHECK-NEXT: [[ADD101:%.*]] = add i32 [[REM85]], [[P_2]] 189; CHECK-NEXT: br i1 false, label [[LOOP_2]], label [[LOOP_3_PREHEADER:%.*]] 190; CHECK: loop.3.preheader: 191; CHECK-NEXT: [[P_2_LCSSA:%.*]] = phi i32 [ [[P_2]], [[LOOP_2]] ] 192; CHECK-NEXT: [[ADD101_LCSSA:%.*]] = phi i32 [ [[ADD101]], [[LOOP_2]] ] 193; CHECK-NEXT: [[TMP0:%.*]] = udiv i32 1, [[P_1]] 194; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i32 [[P_1]], [[TMP0]] 195; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1 196; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[P_2_LCSSA]] 197; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 198; CHECK: vector.ph: 199; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[TMP3]] 200; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 201; CHECK: vector.body: 202; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 203; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 204; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196 205; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 206; CHECK: middle.block: 207; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i32 [[IND_END]], [[TMP3]] 208; CHECK-NEXT: br i1 false, label [[LOOP_4_PREHEADER:%.*]], label [[SCALAR_PH]] 209; CHECK: scalar.ph: 210; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 196, [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_3_PREHEADER]] ] 211; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_3_PREHEADER]] ] 212; CHECK-NEXT: br label [[LOOP_3:%.*]] 213; CHECK: loop.3: 214; CHECK-NEXT: [[IV_3:%.*]] = phi i16 [ [[INC_1:%.*]], [[LOOP_3]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 215; CHECK-NEXT: [[IV_4:%.*]] = phi i32 [ [[SUB93_1:%.*]], [[LOOP_3]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 216; CHECK-NEXT: [[SUB93_1]] = sub i32 [[IV_4]], [[ADD101_LCSSA]] 217; CHECK-NEXT: [[INC_1]] = add i16 [[IV_3]], 1 218; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 198 219; CHECK-NEXT: br i1 [[CMP88_1]], label [[LOOP_3]], label [[LOOP_4_PREHEADER]], !llvm.loop [[LOOP7:![0-9]+]] 220; CHECK: loop.4.preheader: 221; CHECK-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], [[LOOP_3]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] 222; CHECK-NEXT: br label [[LOOP_4:%.*]] 223; CHECK: loop.4: 224; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], [[LOOP_4]] ], [ 0, [[LOOP_4_PREHEADER]] ] 225; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]] 226; CHECK-NEXT: br label [[LOOP_4]] 227; CHECK: loop.1.latch: 228; CHECK-NEXT: br label [[LOOP_1_HEADER]] 229; 230entry: 231 br label %loop.1.header 232 233loop.1.header: 234 %p.1 = phi i32 [ 0, %entry ], [ %sub93.2, %loop.1.latch ] 235 %rem85 = urem i32 1, %p.1 236 br label %loop.2 237 238loop.2: 239 %p.2 = phi i32 [ 1, %loop.1.header ], [ 0, %loop.2 ] 240 %add101 = add i32 %rem85, %p.2 241 br i1 false, label %loop.2, label %loop.3 242 243loop.3: 244 %iv.3 = phi i16 [ 0, %loop.2 ], [ %inc.1, %loop.3 ] 245 %iv.4 = phi i32 [ 0, %loop.2 ], [ %sub93.1, %loop.3 ] 246 %sub93.1 = sub i32 %iv.4, %add101 247 %inc.1 = add i16 %iv.3, 1 248 %cmp88.1 = icmp ult i16 %iv.3, 198 249 br i1 %cmp88.1, label %loop.3, label %loop.4 250 251loop.4: 252 %iv.5 = phi i32 [ 0, %loop.3 ], [ %sub93.2, %loop.4 ] 253 %sub93.2 = sub i32 %iv.5, %iv.4 254 br label %loop.4 255 256loop.1.latch: ; No predecessors! 257 br label %loop.1.header 258} 259