1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S | FileCheck %s 3 4 5; The vectorizer should refuse to fold the tail by masking because 6; %conv is used outside of the loop. Test for this by checking that 7; %n.vec, the vector trip count, is rounded down to the next multiple of 8; 4. If folding the tail, it would have been rounded up instead. 9; Test case for #76069(https://github.com/llvm/llvm-project/issues/76069). 10define i32 @test(ptr %arr, i64 %n) { 11; CHECK-LABEL: define i32 @test( 12; CHECK-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) { 13; CHECK-NEXT: entry: 14; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[N]], 1 15; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER:%.*]], label [[DONE:%.*]] 16; CHECK: preheader: 17; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1 18; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4 19; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 20; CHECK: vector.scevcheck: 21; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], -2 22; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i8 23; CHECK-NEXT: [[TMP8:%.*]] = add i8 2, [[TMP7]] 24; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP8]], 2 25; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP1]], 255 26; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP9]], [[TMP10]] 27; CHECK-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 28; CHECK: vector.ph: 29; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4 30; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 31; CHECK-NEXT: [[IND_END:%.*]] = add i64 1, [[N_VEC]] 32; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i8 33; CHECK-NEXT: [[IND_END1:%.*]] = add i8 1, [[DOTCAST]] 34; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 35; CHECK: vector.body: 36; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 37; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]] 38; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 0 39; CHECK-NEXT: [[TMP17:%.*]] = add nsw i64 [[TMP13]], -1 40; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP17]] 41; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i32 0 42; CHECK-NEXT: store <4 x i32> splat (i32 65), ptr [[TMP19]], align 4 43; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 44; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 45; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 46; CHECK: middle.block: 47; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 48; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[IND_END]], 1 49; CHECK-NEXT: br i1 [[CMP_N]], label [[LOAD_VAL:%.*]], label [[SCALAR_PH]] 50; CHECK: scalar.ph: 51; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1, [[VECTOR_SCEVCHECK]] ], [ 1, [[PREHEADER]] ] 52; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i8 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 1, [[VECTOR_SCEVCHECK]] ], [ 1, [[PREHEADER]] ] 53; CHECK-NEXT: br label [[LOOP:%.*]] 54; CHECK: loop: 55; CHECK-NEXT: [[CONV:%.*]] = phi i64 [ [[CONV2:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 56; CHECK-NEXT: [[I:%.*]] = phi i8 [ [[INC:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ] 57; CHECK-NEXT: [[SUB:%.*]] = add nsw i64 [[CONV]], -1 58; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[SUB]] 59; CHECK-NEXT: store i32 65, ptr [[PTR]], align 4 60; CHECK-NEXT: [[INC]] = add i8 [[I]], 1 61; CHECK-NEXT: [[CONV2]] = zext i8 [[INC]] to i64 62; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[CONV2]], [[N]] 63; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[LOAD_VAL]], !llvm.loop [[LOOP4:![0-9]+]] 64; CHECK: load_val: 65; CHECK-NEXT: [[FINAL:%.*]] = phi i64 [ [[CONV]], [[LOOP]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] 66; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[FINAL]] 67; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR2]], align 4 68; CHECK-NEXT: br label [[DONE]] 69; CHECK: done: 70; CHECK-NEXT: [[VALUE:%.*]] = phi i32 [ [[VAL]], [[LOAD_VAL]] ], [ 0, [[ENTRY:%.*]] ] 71; CHECK-NEXT: ret i32 [[VALUE]] 72; 73entry: 74 %cmp1 = icmp ugt i64 %n, 1 75 br i1 %cmp1, label %preheader, label %done 76 77preheader: 78 br label %loop 79 80loop: 81 %conv = phi i64 [ %conv2, %loop ], [ 1, %preheader ] 82 %i = phi i8 [ %inc, %loop ], [ 1, %preheader ] 83 %sub = add nsw i64 %conv, -1 84 %ptr = getelementptr inbounds i32, ptr %arr, i64 %sub 85 store i32 65, ptr %ptr, align 4 86 %inc = add i8 %i, 1 87 %conv2 = zext i8 %inc to i64 88 %cmp2 = icmp ult i64 %conv2, %n 89 br i1 %cmp2, label %loop, label %load_val, !llvm.loop !0 90 91load_val: 92 %final = phi i64 [ %conv, %loop ] 93 %ptr2 = getelementptr inbounds i32, ptr %arr, i64 %final 94 %val = load i32, ptr %ptr2, align 4 95 br label %done 96 97done: 98 %value = phi i32 [ %val, %load_val ], [ 0, %entry ] 99 ret i32 %value 100 101} 102 103!0 = distinct !{!0, !1, !2, !3} 104!1 = !{!"llvm.loop.unroll.disable"} 105!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true} 106!3 = !{!"llvm.loop.vectorize.enable", i1 true} 107;. 108; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]} 109; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"} 110; CHECK: [[META2]] = !{!"llvm.loop.isvectorized", i32 1} 111; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"} 112; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 113;. 114