1; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -debug-only=vectorutils -disable-output -enable-interleaved-mem-accesses=true 2>&1 | FileCheck %s 2; REQUIRES: asserts 3target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 4target triple = "x86_64-unknown-linux-gnu" 5 6; PR40291 7; The loop does the following operation 3 times: 8; 1. Load x from memory; 9; 2. Store (x + 1) to this memory; 10; 3. if (x < 1), store 0 to this memory. 11 12; When scalar version stores 0 in all locations, the vector version should do 13; the same thing. However, with interleaving it does not honour the WAW dependency between 14; store 0 and store (x + 1) to the same memory. 15; For now, we identify such unsafe dependency and disable adding the 16; store into the interleaved group. 17; In this test case, because we disable adding store into ptr %storeaddr12 and 18; storeaddr22, we create interleaved groups with gaps and 19; disable that interleaved group. So, we are only left with valid interleaved 20; groups. 21 22 23 24 25; CHECK: LV: Analyzing interleaved accesses... 26; CHECK: LV: Creating an interleave group with: store i32 %tmp34, ptr %storeaddr32, align 4 27; CHECK-NEXT: LV: Inserted: store i32 %tmp24, ptr %storeaddr22, align 4 28; CHECK-NEXT: into the interleave group with store i32 %tmp34, ptr %storeaddr32, align 4 29; CHECK-NEXT: LV: Inserted: store i32 %tmp14, ptr %storeaddr12, align 4 30; CHECK-NEXT: into the interleave group with store i32 %tmp34, ptr %storeaddr32, align 4 31; CHECK: LV: Invalidated store group due to dependence between store i32 %tmp24, ptr %storeaddr22, align 4 and store i32 0, ptr %storeaddr22, align 4 32; CHECK-NEXT: LV: Creating an interleave group with: store i32 %tmp24, ptr %storeaddr22, align 4 33; CHECK-NEXT: LV: Inserted: store i32 %tmp14, ptr %storeaddr12, align 4 34; CHECK-NEXT: into the interleave group with store i32 %tmp24, ptr %storeaddr22, align 4 35; CHECK-NEXT: LV: Invalidated store group due to dependence between store i32 %tmp14, ptr %storeaddr12, align 4 and store i32 0, ptr %storeaddr12, align 4 36 37 38define void @test(ptr nonnull align 8 dereferenceable_or_null(24) %arg) { 39bb: 40 %tmp = getelementptr inbounds i8, ptr %arg, i64 16 41 %tmp2 = load ptr, ptr %tmp, align 8 42 %tmp3 = getelementptr inbounds i8, ptr %arg, i64 8 43 %tmp5 = load ptr, ptr %tmp3, align 8 44 %tmp6 = getelementptr inbounds i8, ptr %tmp5, i64 12 45 %tmp8 = getelementptr inbounds i8, ptr %tmp2, i64 12 46 br label %header 47 48header: ; preds = %latch, %bb 49 %tmp10 = phi i64 [ %tmp41, %latch ], [ 3, %bb ] 50 %tmp11 = add nsw i64 %tmp10, -1 51 %storeaddr12 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp11 52 %tmp13 = load i32, ptr %storeaddr12, align 4 53 %tmp14 = add i32 %tmp13, 1 54 store i32 %tmp14, ptr %storeaddr12, align 4 55 %tmp15 = icmp slt i32 %tmp13, 1 56 %tmp16 = xor i1 %tmp15, true 57 %tmp17 = zext i1 %tmp16 to i8 58 %tmp18 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp10 59 store i8 %tmp17, ptr %tmp18, align 1 60 br i1 %tmp15, label %bb19, label %bb20 61 62bb19: ; preds = %header 63 store i32 0, ptr %storeaddr12, align 4 64 br label %bb20 65 66bb20: ; preds = %bb19, %header 67 %tmp21 = add nuw nsw i64 %tmp10, 1 68 %storeaddr22 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp10 69 %tmp23 = load i32, ptr %storeaddr22, align 4 70 %tmp24 = add i32 %tmp23, 1 71 store i32 %tmp24, ptr %storeaddr22, align 4 72 %tmp25 = icmp slt i32 %tmp23, 1 73 %tmp26 = xor i1 %tmp25, true 74 %tmp27 = zext i1 %tmp26 to i8 75 %tmp28 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp21 76 store i8 %tmp27, ptr %tmp28, align 1 77 br i1 %tmp25, label %bb29, label %bb30 78 79bb29: ; preds = %bb20 80 store i32 0, ptr %storeaddr22, align 4 81 br label %bb30 82 83bb30: ; preds = %bb29, %bb20 84 %tmp31 = add nuw nsw i64 %tmp10, 2 85 %storeaddr32 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp21 86 %tmp33 = load i32, ptr %storeaddr32, align 4 87 %tmp34 = add i32 %tmp33, 1 88 store i32 %tmp34, ptr %storeaddr32, align 4 89 %tmp35 = icmp slt i32 %tmp33, 1 90 %tmp36 = xor i1 %tmp35, true 91 %tmp37 = zext i1 %tmp36 to i8 92 %tmp38 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp31 93 store i8 %tmp37, ptr %tmp38, align 1 94 br i1 %tmp35, label %bb39, label %latch 95 96bb39: ; preds = %bb30 97 store i32 0, ptr %storeaddr32, align 4 98 br label %latch 99 100latch: ; preds = %bb39, %bb30 101 %tmp41 = add nuw nsw i64 %tmp10, 3 102 %tmp42 = icmp ugt i64 %tmp31, 67 103 br i1 %tmp42, label %exit, label %header 104 105exit: ; preds = %latch 106 ret void 107} 108