1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -mcpu=skylake-avx512 -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s 3 4; Test case for https://github.com/llvm/llvm-project/issues/102934. 5define void @gep_use_in_dead_block(ptr noalias %dst, ptr %src) { 6; CHECK-LABEL: define void @gep_use_in_dead_block( 7; CHECK-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { 8; CHECK-NEXT: [[ENTRY:.*]]: 9; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 10; CHECK: [[VECTOR_PH]]: 11; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 12; CHECK: [[VECTOR_BODY]]: 13; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 14; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 15; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP0]] 16; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i16, ptr [[TMP4]], i32 0 17; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP5]], align 2 18; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i16> [[WIDE_LOAD]], splat (i16 10) 19; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP6]], splat (i1 true) 20; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[DST]], i64 [[TMP0]] 21; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i16, ptr [[TMP8]], i32 0 22; CHECK-NEXT: call void @llvm.masked.store.v4i16.p0(<4 x i16> zeroinitializer, ptr [[TMP12]], i32 2, <4 x i1> [[TMP7]]) 23; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 24; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 25; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 26; CHECK: [[MIDDLE_BLOCK]]: 27; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]] 28; CHECK: [[SCALAR_PH]]: 29; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 30; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 31; CHECK: [[LOOP_HEADER]]: 32; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 33; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[IV]] 34; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[GEP_SRC]], align 2 35; CHECK-NEXT: [[C:%.*]] = icmp eq i16 [[L]], 10 36; CHECK-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[THEN:.*]] 37; CHECK: [[THEN]]: 38; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i16, ptr [[DST]], i64 [[IV]] 39; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2 40; CHECK-NEXT: br label %[[LOOP_LATCH]] 41; CHECK: [[DEAD:.*]]: 42; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2 43; CHECK-NEXT: br label %[[DEAD]] 44; CHECK: [[LOOP_LATCH]]: 45; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 46; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 99 47; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] 48; CHECK: [[EXIT]]: 49; CHECK-NEXT: ret void 50; 51entry: 52 br label %loop.header 53 54loop.header: 55 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 56 %gep.src = getelementptr i16, ptr %src, i64 %iv 57 %l = load i16, ptr %gep.src 58 %c = icmp eq i16 %l, 10 59 br i1 %c, label %loop.latch, label %then 60 61then: 62 %gep.dst = getelementptr i16, ptr %dst, i64 %iv 63 store i16 0, ptr %gep.dst, align 2 64 br label %loop.latch 65 66dead: 67 store i16 0, ptr %gep.dst, align 2 68 br label %dead 69 70loop.latch: 71 %iv.next = add i64 %iv, 1 72 %ec = icmp eq i64 %iv.next, 99 73 br i1 %ec, label %exit, label %loop.header 74 75exit: 76 ret void 77} 78 79define void @gep_use_outside_loop(ptr noalias %dst, ptr %src) { 80; CHECK-LABEL: define void @gep_use_outside_loop( 81; CHECK-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) #[[ATTR0]] { 82; CHECK-NEXT: [[ENTRY:.*]]: 83; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 84; CHECK: [[VECTOR_PH]]: 85; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 86; CHECK: [[VECTOR_BODY]]: 87; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 88; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 89; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 90; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i16, ptr [[DST]], <4 x i64> [[VEC_IND]] 91; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP0]] 92; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr [[TMP2]], i32 0 93; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP3]], align 2 94; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i16> [[WIDE_LOAD]], splat (i16 10) 95; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true) 96; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x ptr> [[TMP1]], i32 0 97; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i16, ptr [[TMP6]], i32 0 98; CHECK-NEXT: call void @llvm.masked.store.v4i16.p0(<4 x i16> zeroinitializer, ptr [[TMP7]], i32 2, <4 x i1> [[TMP5]]) 99; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 100; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 101; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 102; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 103; CHECK: [[MIDDLE_BLOCK]]: 104; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x ptr> [[TMP1]], i32 3 105; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]] 106; CHECK: [[SCALAR_PH]]: 107; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 108; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 109; CHECK: [[LOOP_HEADER]]: 110; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 111; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i16, ptr [[DST]], i64 [[IV]] 112; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[IV]] 113; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[GEP_SRC]], align 2 114; CHECK-NEXT: [[C:%.*]] = icmp eq i16 [[L]], 10 115; CHECK-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[THEN:.*]] 116; CHECK: [[THEN]]: 117; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2 118; CHECK-NEXT: br label %[[LOOP_LATCH]] 119; CHECK: [[LOOP_LATCH]]: 120; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 121; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 99 122; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] 123; CHECK: [[EXIT]]: 124; CHECK-NEXT: [[GEP_DST_LCSSA:%.*]] = phi ptr [ [[GEP_DST]], %[[LOOP_LATCH]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ] 125; CHECK-NEXT: store i16 0, ptr [[GEP_DST_LCSSA]], align 2 126; CHECK-NEXT: ret void 127; 128entry: 129 br label %loop.header 130 131loop.header: 132 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 133 %gep.dst = getelementptr i16, ptr %dst, i64 %iv 134 %gep.src = getelementptr i16, ptr %src, i64 %iv 135 %l = load i16, ptr %gep.src 136 %c = icmp eq i16 %l, 10 137 br i1 %c, label %loop.latch, label %then 138 139then: 140 store i16 0, ptr %gep.dst, align 2 141 br label %loop.latch 142 143loop.latch: 144 %iv.next = add i64 %iv, 1 145 %ec = icmp eq i64 %iv.next, 99 146 br i1 %ec, label %exit, label %loop.header 147 148exit: 149 store i16 0, ptr %gep.dst, align 2 150 ret void 151} 152;. 153; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 154; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 155; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 156; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 157; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 158; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} 159;. 160