1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=riscv64 -mattr=+zve32x -passes=loop-vectorize < %s | FileCheck %s 3 4define void @small_trip_count_min_vlen_128(ptr nocapture %a) nounwind vscale_range(4,1024) { 5; CHECK-LABEL: @small_trip_count_min_vlen_128( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 8; CHECK: vector.ph: 9; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32() 10; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 1 11; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 4, [[TMP1]] 12; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], [[TMP0]] 13; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]] 14; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32() 15; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 16; CHECK: vector.body: 17; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 4) 18; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP4:%.*]], i32 0 19; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 20; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 1 x i32> @llvm.masked.load.nxv1i32.p0(ptr [[TMP7]], i32 4, <vscale x 1 x i1> [[ACTIVE_LANE_MASK]], <vscale x 1 x i32> poison) 21; CHECK-NEXT: [[TMP6:%.*]] = add nsw <vscale x 1 x i32> [[WIDE_MASKED_LOAD]], splat (i32 1) 22; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 23; CHECK-NEXT: call void @llvm.masked.store.nxv1i32.p0(<vscale x 1 x i32> [[TMP6]], ptr [[TMP8]], i32 4, <vscale x 1 x i1> [[ACTIVE_LANE_MASK]]) 24; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]] 25; CHECK: middle.block: 26; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 27; CHECK: scalar.ph: 28; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 29; CHECK-NEXT: br label [[LOOP:%.*]] 30; CHECK: loop: 31; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 32; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[IV]] 33; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4 34; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[V]], 1 35; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP]], align 4 36; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 37; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 3 38; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP0:![0-9]+]] 39; CHECK: exit: 40; CHECK-NEXT: ret void 41; 42entry: 43 br label %loop 44 45loop: 46 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] 47 %gep = getelementptr inbounds i32, ptr %a, i32 %iv 48 %v = load i32, ptr %gep, align 4 49 %add = add nsw i32 %v, 1 50 store i32 %add, ptr %gep, align 4 51 %iv.next = add i32 %iv, 1 52 %cond = icmp eq i32 %iv, 3 53 br i1 %cond, label %exit, label %loop 54 55exit: 56 ret void 57} 58 59define void @small_trip_count_min_vlen_32(ptr nocapture %a) nounwind vscale_range(1,1024) { 60; CHECK-LABEL: @small_trip_count_min_vlen_32( 61; CHECK-NEXT: entry: 62; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 63; CHECK: vector.ph: 64; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32() 65; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], 4 66; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 1 67; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 4, [[TMP2]] 68; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], [[TMP1]] 69; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]] 70; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32() 71; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], 4 72; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 73; CHECK: vector.body: 74; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4) 75; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP6:%.*]], i32 0 76; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i32 0 77; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr [[TMP9]], i32 4, <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], <vscale x 4 x i32> poison) 78; CHECK-NEXT: [[TMP8:%.*]] = add nsw <vscale x 4 x i32> [[WIDE_MASKED_LOAD]], splat (i32 1) 79; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i32 0 80; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP8]], ptr [[TMP10]], i32 4, <vscale x 4 x i1> [[ACTIVE_LANE_MASK]]) 81; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]] 82; CHECK: middle.block: 83; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 84; CHECK: scalar.ph: 85; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 86; CHECK-NEXT: br label [[LOOP:%.*]] 87; CHECK: loop: 88; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 89; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i32 [[IV]] 90; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4 91; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[V]], 1 92; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP]], align 4 93; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 94; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 3 95; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 96; CHECK: exit: 97; CHECK-NEXT: ret void 98; 99entry: 100 br label %loop 101 102loop: 103 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] 104 %gep = getelementptr inbounds i32, ptr %a, i32 %iv 105 %v = load i32, ptr %gep, align 4 106 %add = add nsw i32 %v, 1 107 store i32 %add, ptr %gep, align 4 108 %iv.next = add i32 %iv, 1 109 %cond = icmp eq i32 %iv, 3 110 br i1 %cond, label %exit, label %loop 111 112exit: 113 ret void 114} 115