1; REQUIRES: asserts 2; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \ 3; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \ 4; RUN: -riscv-v-vector-bits-min=128 -force-vector-width=1 \ 5; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SCALAR 6; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \ 7; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \ 8; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=1 \ 9; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1 10; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \ 11; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \ 12; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=2 \ 13; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2 14; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \ 15; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \ 16; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=4 \ 17; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4 18; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \ 19; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \ 20; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=8 \ 21; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8 22 23define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) { 24; CHECK-LABEL: add 25; CHECK-SCALAR: LV(REG): Found max usage: 2 item 26; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 27; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers 28; CHECK-SCALAR-NEXT: LV(REG): Found invariant usage: 1 item 29; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 30; CHECK-LMUL1: LV(REG): Found max usage: 2 item 31; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 32; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers 33; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item 34; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 35; CHECK-LMUL2: LV(REG): Found max usage: 2 item 36; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 37; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers 38; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item 39; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 40; CHECK-LMUL4: LV(REG): Found max usage: 2 item 41; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 42; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers 43; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item 44; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 45; CHECK-LMUL8: LV(REG): Found max usage: 2 item 46; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 47; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 16 registers 48; CHECK-LMUL8-NEXT: LV(REG): Found invariant usage: 1 item 49; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 50 51entry: 52 %conv = zext i32 %size to i64 53 %cmp10.not = icmp eq i32 %size, 0 54 br i1 %cmp10.not, label %for.cond.cleanup, label %for.body 55 56for.cond.cleanup: 57 ret void 58 59for.body: 60 %i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ] 61 %arrayidx = getelementptr inbounds float, ptr %src1, i64 %i.011 62 %0 = load float, ptr %arrayidx, align 4 63 %arrayidx2 = getelementptr inbounds float, ptr %src2, i64 %i.011 64 %1 = load float, ptr %arrayidx2, align 4 65 %add = fadd float %0, %1 66 %arrayidx3 = getelementptr inbounds float, ptr %result, i64 %i.011 67 store float %add, ptr %arrayidx3, align 4 68 %add4 = add nuw nsw i64 %i.011, 1 69 %exitcond.not = icmp eq i64 %add4, %conv 70 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body 71} 72 73define void @goo(ptr nocapture noundef %a, i32 noundef signext %n) { 74; CHECK-LABEL: goo 75; CHECK-SCALAR: LV(REG): Found max usage: 1 item 76; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers 77; CHECK-LMUL1: LV(REG): Found max usage: 2 item 78; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 79; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 1 registers 80; CHECK-LMUL2: LV(REG): Found max usage: 2 item 81; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 82; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers 83; CHECK-LMUL4: LV(REG): Found max usage: 2 item 84; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 85; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers 86; CHECK-LMUL8: LV(REG): Found max usage: 2 item 87; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 88; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers 89entry: 90 %cmp3 = icmp sgt i32 %n, 0 91 br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup 92 93for.body.preheader: ; preds = %entry 94 %wide.trip.count = zext i32 %n to i64 95 br label %for.body 96 97for.cond.cleanup.loopexit: ; preds = %for.body 98 br label %for.cond.cleanup 99 100for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry 101 ret void 102 103for.body: ; preds = %for.body.preheader, %for.body 104 %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 105 %arrayidx = getelementptr inbounds ptr, ptr %a, i64 %indvars.iv 106 %0 = load ptr, ptr %arrayidx, align 8 107 %add.ptr = getelementptr inbounds i32, ptr %0, i64 1 108 store ptr %add.ptr, ptr %arrayidx, align 8 109 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 110 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count 111 br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body 112} 113