1; REQUIRES: asserts 2; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfh -debug-only=loop-vectorize --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFH 3; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfhmin -debug-only=loop-vectorize --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFHMIN 4 5define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) { 6; CHECK-LABEL: add 7; ZVFH: LV(REG): Found max usage: 2 item 8; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 9; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers 10; ZVFH-NEXT: LV(REG): Found invariant usage: 1 item 11; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 12; ZVFHMIN: LV(REG): Found max usage: 2 item 13; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers 14; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers 15; ZVFHMIN-NEXT: LV(REG): Found invariant usage: 1 item 16; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers 17 18entry: 19 %conv = zext i32 %size to i64 20 %cmp10.not = icmp eq i32 %size, 0 21 br i1 %cmp10.not, label %for.cond.cleanup, label %for.body 22 23for.cond.cleanup: 24 ret void 25 26for.body: 27 %i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ] 28 %arrayidx = getelementptr inbounds half, ptr %src1, i64 %i.011 29 %0 = load half, ptr %arrayidx, align 4 30 %arrayidx2 = getelementptr inbounds half, ptr %src2, i64 %i.011 31 %1 = load half, ptr %arrayidx2, align 4 32 %add = fadd half %0, %1 33 %arrayidx3 = getelementptr inbounds half, ptr %result, i64 %i.011 34 store half %add, ptr %arrayidx3, align 4 35 %add4 = add nuw nsw i64 %i.011, 1 36 %exitcond.not = icmp eq i64 %add4, %conv 37 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body 38} 39