xref: /llvm-project/llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-zve32x.ll (revision e39f6c1844fab59c638d8059a6cf139adb42279a)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+zve32x,+zvl1024b -S | FileCheck %s
3
4; This element type isn't a supported SEW so this shouldn't be interleaved
5define void @load_store_zve32x(ptr %p) {
6; CHECK-LABEL: @load_store_zve32x(
7; CHECK-NEXT:  entry:
8; CHECK-NEXT:    br label [[LOOP:%.*]]
9; CHECK:       loop:
10; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[NEXTI:%.*]], [[LOOP]] ]
11; CHECK-NEXT:    [[OFFSET0:%.*]] = shl i64 [[I]], 1
12; CHECK-NEXT:    [[Q0:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[OFFSET0]]
13; CHECK-NEXT:    [[X0:%.*]] = load i64, ptr [[Q0]], align 8
14; CHECK-NEXT:    [[Y0:%.*]] = add i64 [[X0]], 1
15; CHECK-NEXT:    store i64 [[Y0]], ptr [[Q0]], align 8
16; CHECK-NEXT:    [[OFFSET1:%.*]] = add i64 [[OFFSET0]], 1
17; CHECK-NEXT:    [[Q1:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET1]]
18; CHECK-NEXT:    [[X1:%.*]] = load i64, ptr [[Q1]], align 8
19; CHECK-NEXT:    [[Y1:%.*]] = add i64 [[X1]], 2
20; CHECK-NEXT:    store i64 [[Y1]], ptr [[Q1]], align 8
21; CHECK-NEXT:    [[NEXTI]] = add i64 [[I]], 1
22; CHECK-NEXT:    [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024
23; CHECK-NEXT:    br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
24; CHECK:       exit:
25; CHECK-NEXT:    ret void
26;
27entry:
28  br label %loop
29loop:
30  %i = phi i64 [0, %entry], [%nexti, %loop]
31
32  %offset0 = shl i64 %i, 1
33  %q0 = getelementptr i64, ptr %p, i64 %offset0
34  %x0 = load i64, ptr %q0
35  %y0 = add i64 %x0, 1
36  store i64 %y0, ptr %q0
37
38  %offset1 = add i64 %offset0, 1
39  %q1 = getelementptr i64, ptr %p, i64 %offset1
40  %x1 = load i64, ptr %q1
41  %y1 = add i64 %x1, 2
42  store i64 %y1, ptr %q1
43
44  %nexti = add i64 %i, 1
45  %done = icmp eq i64 %nexti, 1024
46  br i1 %done, label %exit, label %loop
47exit:
48  ret void
49}
50