1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -p loop-vectorize -mtriple riscv64-linux-gnu -mattr=+v,+f -S %s | FileCheck %s 3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" 5 6; Test with a dead load in the loop, from 7; https://github.com/llvm/llvm-project/issues/99701 8define void @dead_load(ptr %p, i16 %start) { 9; CHECK-LABEL: define void @dead_load( 10; CHECK-SAME: ptr [[P:%.*]], i16 [[START:%.*]]) #[[ATTR0:[0-9]+]] { 11; CHECK-NEXT: [[ENTRY:.*]]: 12; CHECK-NEXT: [[START_EXT:%.*]] = sext i16 [[START]] to i64 13; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[START_EXT]], i64 111) 14; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[SMAX]], [[START_EXT]] 15; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 1) 16; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[SMAX]], [[UMIN]] 17; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START_EXT]] 18; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP2]], 3 19; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[UMIN]], [[TMP3]] 20; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 1 21; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() 22; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 8 23; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP5]], [[TMP7]] 24; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 25; CHECK: [[VECTOR_PH]]: 26; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64() 27; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP8]], 8 28; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP5]], [[TMP9]] 29; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 30; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 [[N_MOD_VF]] 31; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP5]], [[TMP11]] 32; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64() 33; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 8 34; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[N_VEC]], 3 35; CHECK-NEXT: [[IND_END:%.*]] = add i64 [[START_EXT]], [[TMP18]] 36; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[START_EXT]], i64 0 37; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 38; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64() 39; CHECK-NEXT: [[TMP17:%.*]] = mul <vscale x 8 x i64> [[TMP15]], splat (i64 3) 40; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 8 x i64> [[DOTSPLAT]], [[TMP17]] 41; CHECK-NEXT: [[TMP20:%.*]] = mul i64 3, [[TMP14]] 42; CHECK-NEXT: [[DOTSPLATINSERT1:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP20]], i64 0 43; CHECK-NEXT: [[DOTSPLAT2:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT1]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 44; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 45; CHECK: [[VECTOR_BODY]]: 46; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 47; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 48; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i16, ptr [[P]], <vscale x 8 x i64> [[VEC_IND]] 49; CHECK-NEXT: call void @llvm.masked.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> [[TMP21]], i32 2, <vscale x 8 x i1> splat (i1 true)) 50; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP14]] 51; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT2]] 52; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 53; CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 54; CHECK: [[MIDDLE_BLOCK]]: 55; CHECK-NEXT: br label %[[SCALAR_PH]] 56; CHECK: [[SCALAR_PH]]: 57; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START_EXT]], %[[ENTRY]] ] 58; CHECK-NEXT: br label %[[LOOP:.*]] 59; CHECK: [[LOOP]]: 60; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] 61; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr [[P]], i64 [[IV]] 62; CHECK-NEXT: store i16 0, ptr [[GEP]], align 2 63; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[GEP]], align 2 64; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 3 65; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV]], 111 66; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]] 67; CHECK: [[EXIT]]: 68; CHECK-NEXT: ret void 69; 70entry: 71 %start.ext = sext i16 %start to i64 72 br label %loop 73 74loop: 75 %iv = phi i64 [ %start.ext, %entry ], [ %iv.next, %loop ] 76 %gep = getelementptr i16, ptr %p, i64 %iv 77 store i16 0, ptr %gep, align 2 78 %l = load i16, ptr %gep, align 2 79 %iv.next = add i64 %iv, 3 80 %cmp = icmp slt i64 %iv, 111 81 br i1 %cmp, label %loop, label %exit 82 83exit: 84 ret void 85} 86 87; Test case for https://github.com/llvm/llvm-project/issues/100464. 88; Loop with a live-out %l and scalar epilogue required due to an interleave 89; group. As the scalar epilogue is required the live-out is fed from the scalar 90; epilogue and dead in the vector loop. 91define i8 @dead_live_out_due_to_scalar_epilogue_required(ptr %src, ptr %dst) { 92; CHECK-LABEL: define i8 @dead_live_out_due_to_scalar_epilogue_required( 93; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] { 94; CHECK-NEXT: [[ENTRY:.*]]: 95; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32() 96; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], 4 97; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 8, i32 [[TMP1]]) 98; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 252, [[TMP2]] 99; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] 100; CHECK: [[VECTOR_MEMCHECK]]: 101; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 1005 102; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 1005 103; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]] 104; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]] 105; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 106; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] 107; CHECK: [[VECTOR_PH]]: 108; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32() 109; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], 4 110; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 252, [[TMP4]] 111; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[N_MOD_VF]], 0 112; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i32 [[TMP4]], i32 [[N_MOD_VF]] 113; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 252, [[TMP6]] 114; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vscale.i32() 115; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 4 116; CHECK-NEXT: [[IND_END:%.*]] = mul i32 [[N_VEC]], 4 117; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32() 118; CHECK-NEXT: [[TMP11:%.*]] = mul <vscale x 4 x i32> [[TMP9]], splat (i32 4) 119; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i32> zeroinitializer, [[TMP11]] 120; CHECK-NEXT: [[TMP14:%.*]] = mul i32 4, [[TMP8]] 121; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP14]], i64 0 122; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 123; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 124; CHECK: [[VECTOR_BODY]]: 125; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 126; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 127; CHECK-NEXT: [[TMP15:%.*]] = sext <vscale x 4 x i32> [[VEC_IND]] to <vscale x 4 x i64> 128; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[DST]], <vscale x 4 x i64> [[TMP15]] 129; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i8.nxv4p0(<vscale x 4 x i8> zeroinitializer, <vscale x 4 x ptr> [[TMP16]], i32 1, <vscale x 4 x i1> splat (i1 true)), !alias.scope [[META4:![0-9]+]], !noalias [[META7:![0-9]+]] 130; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP8]] 131; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i32> [[VEC_IND]], [[DOTSPLAT]] 132; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 133; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] 134; CHECK: [[MIDDLE_BLOCK]]: 135; CHECK-NEXT: br label %[[SCALAR_PH]] 136; CHECK: [[SCALAR_PH]]: 137; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_MEMCHECK]] ], [ 0, %[[ENTRY]] ] 138; CHECK-NEXT: br label %[[LOOP:.*]] 139; CHECK: [[LOOP]]: 140; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] 141; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[IV]] to i64 142; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IDXPROM]] 143; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 144; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IDXPROM]] 145; CHECK-NEXT: store i8 0, ptr [[GEP_DST]], align 1 146; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 4 147; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IV]], 1001 148; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP10:![0-9]+]] 149; CHECK: [[EXIT]]: 150; CHECK-NEXT: [[R:%.*]] = phi i8 [ [[L]], %[[LOOP]] ] 151; CHECK-NEXT: ret i8 [[R]] 152; 153entry: 154 br label %loop 155 156loop: 157 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 158 %idxprom = sext i32 %iv to i64 159 %gep.src = getelementptr i8, ptr %src, i64 %idxprom 160 %l = load i8, ptr %gep.src, align 1 161 %gep.dst = getelementptr i8, ptr %dst, i64 %idxprom 162 store i8 0, ptr %gep.dst, align 1 163 %iv.next = add i32 %iv, 4 164 %cmp = icmp ult i32 %iv, 1001 165 br i1 %cmp, label %loop, label %exit 166 167exit: 168 %r = phi i8 [ %l, %loop ] 169 ret i8 %r 170} 171 172declare i16 @llvm.umax.i16(i16, i16) 173 174; Test case for https://github.com/llvm/llvm-project/issues/106780. 175define i32 @cost_of_exit_branch_and_cond_insts(ptr %a, ptr %b, i1 %c, i16 %x) #0 { 176; CHECK-LABEL: define i32 @cost_of_exit_branch_and_cond_insts( 177; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i1 [[C:%.*]], i16 [[X:%.*]]) #[[ATTR2:[0-9]+]] { 178; CHECK-NEXT: [[ENTRY:.*]]: 179; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[X]] to i32 180; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP0]], i32 111) 181; CHECK-NEXT: [[TMP1:%.*]] = sub i32 770, [[UMAX3]] 182; CHECK-NEXT: [[SMAX4:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0) 183; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[SMAX4]], 1 184; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP2]], 24 185; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] 186; CHECK: [[VECTOR_MEMCHECK]]: 187; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 1 188; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[X]] to i32 189; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP3]], i32 111) 190; CHECK-NEXT: [[TMP4:%.*]] = sub i32 770, [[UMAX1]] 191; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP4]], i32 0) 192; CHECK-NEXT: [[TMP5:%.*]] = zext nneg i32 [[SMAX]] to i64 193; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[TMP5]], 2 194; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 4 195; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP7]] 196; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP2]] 197; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[B]], [[SCEVGEP]] 198; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 199; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] 200; CHECK: [[VECTOR_PH]]: 201; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 8 202; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[N_MOD_VF]], 0 203; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 8, i32 [[N_MOD_VF]] 204; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[TMP9]] 205; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i1> poison, i1 [[C]], i64 0 206; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i1> [[BROADCAST_SPLATINSERT]], <8 x i1> poison, <8 x i32> zeroinitializer 207; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 208; CHECK: [[VECTOR_BODY]]: 209; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE18:.*]] ] 210; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 0 211; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[B]], i32 [[TMP10]] 212; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] 213; CHECK: [[PRED_STORE_IF]]: 214; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11:![0-9]+]], !noalias [[META14:![0-9]+]] 215; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]] 216; CHECK: [[PRED_STORE_CONTINUE]]: 217; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]] 218; CHECK: [[PRED_STORE_IF5]]: 219; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 220; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]] 221; CHECK: [[PRED_STORE_CONTINUE6]]: 222; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]] 223; CHECK: [[PRED_STORE_IF7]]: 224; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 225; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]] 226; CHECK: [[PRED_STORE_CONTINUE8]]: 227; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]] 228; CHECK: [[PRED_STORE_IF9]]: 229; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 230; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]] 231; CHECK: [[PRED_STORE_CONTINUE10]]: 232; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]] 233; CHECK: [[PRED_STORE_IF11]]: 234; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 235; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]] 236; CHECK: [[PRED_STORE_CONTINUE12]]: 237; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]] 238; CHECK: [[PRED_STORE_IF13]]: 239; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 240; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]] 241; CHECK: [[PRED_STORE_CONTINUE14]]: 242; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]] 243; CHECK: [[PRED_STORE_IF15]]: 244; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 245; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]] 246; CHECK: [[PRED_STORE_CONTINUE16]]: 247; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18]] 248; CHECK: [[PRED_STORE_IF17]]: 249; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]] 250; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]] 251; CHECK: [[PRED_STORE_CONTINUE18]]: 252; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP11]], i32 0 253; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP20]], i32 4, <8 x i1> [[BROADCAST_SPLAT]]), !alias.scope [[META14]] 254; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 255; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 256; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 257; CHECK: [[MIDDLE_BLOCK]]: 258; CHECK-NEXT: br label %[[SCALAR_PH]] 259; CHECK: [[SCALAR_PH]]: 260; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_MEMCHECK]] ], [ 0, %[[ENTRY]] ] 261; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 262; CHECK: [[LOOP_HEADER]]: 263; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 264; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_EXITING:.*]] 265; CHECK: [[THEN]]: 266; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[IV]] 267; CHECK-NEXT: store i1 false, ptr [[A]], align 1 268; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4 269; CHECK-NEXT: br label %[[LOOP_EXITING]] 270; CHECK: [[LOOP_EXITING]]: 271; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 272; CHECK-NEXT: [[UMAX:%.*]] = tail call i16 @llvm.umax.i16(i16 [[X]], i16 111) 273; CHECK-NEXT: [[UMAX_EXT:%.*]] = zext i16 [[UMAX]] to i32 274; CHECK-NEXT: [[SUB:%.*]] = sub i32 770, [[UMAX_EXT]] 275; CHECK-NEXT: [[EC:%.*]] = icmp slt i32 [[IV]], [[SUB]] 276; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_LATCH]], label %[[EXIT:.*]] 277; CHECK: [[LOOP_LATCH]]: 278; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP17:![0-9]+]] 279; CHECK: [[EXIT]]: 280; CHECK-NEXT: br label %[[RETURN:.*]] 281; CHECK: [[RETURN]]: 282; CHECK-NEXT: ret i32 0 283; 284entry: 285 br label %loop.header 286 287loop.header: 288 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] 289 br i1 %c, label %then, label %loop.exiting 290 291then: 292 %gep = getelementptr inbounds i32, ptr %b, i32 %iv 293 store i1 false, ptr %a, align 1 294 store i32 0, ptr %gep, align 4 295 br label %loop.exiting 296 297loop.exiting: 298 %iv.next = add i32 %iv, 1 299 %umax = tail call i16 @llvm.umax.i16(i16 %x, i16 111) 300 %umax.ext = zext i16 %umax to i32 301 %sub = sub i32 770, %umax.ext 302 %ec = icmp slt i32 %iv, %sub 303 br i1 %ec, label %loop.latch, label %exit 304 305loop.latch: 306 br label %loop.header 307 308exit: 309 br label %return 310 311return: 312 ret i32 0 313} 314 315; Test case for https://github.com/llvm/llvm-project/issues/107473. 316define void @test_phi_in_latch_redundant(ptr %dst, i32 %a) { 317; CHECK-LABEL: define void @test_phi_in_latch_redundant( 318; CHECK-SAME: ptr [[DST:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { 319; CHECK-NEXT: [[ENTRY:.*]]: 320; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 321; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2 322; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 37, [[TMP1]] 323; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 324; CHECK: [[VECTOR_PH]]: 325; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 326; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 2 327; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 37, [[TMP3]] 328; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 37, [[N_MOD_VF]] 329; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 330; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 331; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], 9 332; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[A]], i64 0 333; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 334; CHECK-NEXT: [[TMP10:%.*]] = xor <vscale x 2 x i32> [[BROADCAST_SPLAT]], splat (i32 -1) 335; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64() 336; CHECK-NEXT: [[TMP8:%.*]] = mul <vscale x 2 x i64> [[TMP6]], splat (i64 9) 337; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP8]] 338; CHECK-NEXT: [[TMP9:%.*]] = mul i64 9, [[TMP5]] 339; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP9]], i64 0 340; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 341; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 342; CHECK: [[VECTOR_BODY]]: 343; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 344; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 345; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[DST]], <vscale x 2 x i64> [[VEC_IND]] 346; CHECK-NEXT: call void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32> [[TMP10]], <vscale x 2 x ptr> [[TMP11]], i32 4, <vscale x 2 x i1> splat (i1 true)) 347; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] 348; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[DOTSPLAT]] 349; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 350; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] 351; CHECK: [[MIDDLE_BLOCK]]: 352; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 37, [[N_VEC]] 353; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 354; CHECK: [[SCALAR_PH]]: 355; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 356; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 357; CHECK: [[LOOP_HEADER]]: 358; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 359; CHECK-NEXT: br i1 false, label %[[LOOP_LATCH]], label %[[THEN:.*]] 360; CHECK: [[THEN]]: 361; CHECK-NEXT: [[NOT_A:%.*]] = xor i32 [[A]], -1 362; CHECK-NEXT: br label %[[LOOP_LATCH]] 363; CHECK: [[LOOP_LATCH]]: 364; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[NOT_A]], %[[THEN]] ], [ 0, %[[LOOP_HEADER]] ] 365; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV]] 366; CHECK-NEXT: store i32 [[P]], ptr [[GEP]], align 4 367; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 9 368; CHECK-NEXT: [[EC:%.*]] = icmp slt i64 [[IV]], 322 369; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT]], !llvm.loop [[LOOP19:![0-9]+]] 370; CHECK: [[EXIT]]: 371; CHECK-NEXT: ret void 372; 373entry: 374 br label %loop.header 375 376loop.header: 377 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 378 br i1 false, label %loop.latch, label %then 379 380then: 381 %not.a = xor i32 %a, -1 382 br label %loop.latch 383 384loop.latch: 385 %p = phi i32 [ %not.a, %then ], [ 0, %loop.header ] 386 %gep = getelementptr i32, ptr %dst, i64 %iv 387 store i32 %p, ptr %gep, align 4 388 %iv.next = add i64 %iv, 9 389 %ec = icmp slt i64 %iv, 322 390 br i1 %ec, label %loop.header, label %exit 391 392exit: 393 ret void 394} 395 396; Test for https://github.com/llvm/llvm-project/issues/108098. 397define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %src, ptr noalias %dst) #0 { 398; CHECK-LABEL: define void @gather_interleave_group_with_dead_insert_pos( 399; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2]] { 400; CHECK-NEXT: [[ENTRY:.*]]: 401; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) 402; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[SMAX]], 1 403; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1 404; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 405; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() 406; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 4 407; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], [[TMP4]] 408; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 409; CHECK: [[VECTOR_PH]]: 410; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() 411; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 4 412; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], [[TMP6]] 413; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] 414; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() 415; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 4 416; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[N_VEC]], 2 417; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() 418; CHECK-NEXT: [[TMP11:%.*]] = mul <vscale x 4 x i64> [[TMP9]], splat (i64 2) 419; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i64> zeroinitializer, [[TMP11]] 420; CHECK-NEXT: [[TMP12:%.*]] = mul i64 2, [[TMP8]] 421; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP12]], i64 0 422; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 423; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 424; CHECK: [[VECTOR_BODY]]: 425; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 426; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 427; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 428; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 0 429; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]] 430; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i8>, ptr [[TMP15]], align 1 431; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> [[WIDE_VEC]]) 432; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[STRIDED_VEC]], 0 433; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[STRIDED_VEC]], 1 434; CHECK-NEXT: [[TMP18:%.*]] = zext <vscale x 4 x i8> [[TMP17]] to <vscale x 4 x i32> 435; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[DST]], <vscale x 4 x i64> [[VEC_IND]] 436; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP18]], <vscale x 4 x ptr> [[TMP19]], i32 4, <vscale x 4 x i1> splat (i1 true)) 437; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] 438; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[VEC_IND]], [[DOTSPLAT]] 439; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 440; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] 441; CHECK: [[MIDDLE_BLOCK]]: 442; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] 443; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 444; CHECK: [[SCALAR_PH]]: 445; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 446; CHECK-NEXT: br label %[[LOOP:.*]] 447; CHECK: [[LOOP]]: 448; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 449; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] 450; CHECK-NEXT: [[L_DEAD:%.*]] = load i8, ptr [[GEP_SRC_0]], align 1 451; CHECK-NEXT: [[IV_1:%.*]] = add i64 [[IV]], 1 452; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV_1]] 453; CHECK-NEXT: [[L_1:%.*]] = load i8, ptr [[GEP_SRC_1]], align 1 454; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[L_1]] to i32 455; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV]] 456; CHECK-NEXT: store i32 [[EXT]], ptr [[GEP_DST]], align 4 457; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2 458; CHECK-NEXT: [[EC:%.*]] = icmp slt i64 [[IV]], [[N]] 459; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP21:![0-9]+]] 460; CHECK: [[EXIT]]: 461; CHECK-NEXT: ret void 462; 463entry: 464 br label %loop 465 466loop: 467 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] 468 %gep.src.0 = getelementptr i8, ptr %src, i64 %iv 469 %l.dead = load i8, ptr %gep.src.0, align 1 470 %iv.1 = add i64 %iv, 1 471 %gep.src.1 = getelementptr i8, ptr %src, i64 %iv.1 472 %l.1 = load i8, ptr %gep.src.1, align 1 473 %ext = zext i8 %l.1 to i32 474 %gep.dst = getelementptr i32, ptr %dst, i64 %iv 475 store i32 %ext, ptr %gep.dst, align 4 476 %iv.next = add nsw i64 %iv, 2 477 %ec = icmp slt i64 %iv, %N 478 br i1 %ec, label %loop, label %exit 479 480exit: 481 ret void 482} 483 484attributes #0 = { "target-features"="+64bit,+v" } 485 486;. 487; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 488; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 489; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 490; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 491; CHECK: [[META4]] = !{[[META5:![0-9]+]]} 492; CHECK: [[META5]] = distinct !{[[META5]], [[META6:![0-9]+]]} 493; CHECK: [[META6]] = distinct !{[[META6]], !"LVerDomain"} 494; CHECK: [[META7]] = !{[[META8:![0-9]+]]} 495; CHECK: [[META8]] = distinct !{[[META8]], [[META6]]} 496; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} 497; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} 498; CHECK: [[META11]] = !{[[META12:![0-9]+]]} 499; CHECK: [[META12]] = distinct !{[[META12]], [[META13:![0-9]+]]} 500; CHECK: [[META13]] = distinct !{[[META13]], !"LVerDomain"} 501; CHECK: [[META14]] = !{[[META15:![0-9]+]]} 502; CHECK: [[META15]] = distinct !{[[META15]], [[META13]]} 503; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} 504; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]} 505; CHECK: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]} 506; CHECK: [[LOOP19]] = distinct !{[[LOOP19]], [[META2]], [[META1]]} 507; CHECK: [[LOOP20]] = distinct !{[[LOOP20]], [[META1]], [[META2]]} 508; CHECK: [[LOOP21]] = distinct !{[[LOOP21]], [[META2]], [[META1]]} 509;. 510