1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -p loop-vectorize -S %s | FileCheck %s 3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" 5target triple = "riscv64-unknown-linux-gnu" 6 7; Test case for https://github.com/llvm/llvm-project/issues/111874. 8define i32 @any_of_reduction_used_in_blend(ptr %src, i64 %N, i1 %c.0, i1 %c.1) #0 { 9; CHECK-LABEL: define i32 @any_of_reduction_used_in_blend( 10; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]], i1 [[C_0:%.*]], i1 [[C_1:%.*]]) #[[ATTR0:[0-9]+]] { 11; CHECK-NEXT: [[ENTRY:.*]]: 12; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 13; CHECK: [[LOOP_HEADER]]: 14; CHECK-NEXT: [[ANY_OF_RED:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ANY_OF_RED_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 15; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH]] ] 16; CHECK-NEXT: br i1 [[C_0]], label %[[LOOP_LATCH]], label %[[ELSE_1:.*]] 17; CHECK: [[ELSE_1]]: 18; CHECK-NEXT: br i1 [[C_1]], label %[[LOOP_LATCH]], label %[[ELSE_2:.*]] 19; CHECK: [[ELSE_2]]: 20; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[SRC]], align 8 21; CHECK-NEXT: [[C_2:%.*]] = icmp eq ptr [[L]], null 22; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C_2]], i32 0, i32 [[ANY_OF_RED]] 23; CHECK-NEXT: br label %[[LOOP_LATCH]] 24; CHECK: [[LOOP_LATCH]]: 25; CHECK-NEXT: [[ANY_OF_RED_NEXT]] = phi i32 [ [[ANY_OF_RED]], %[[LOOP_HEADER]] ], [ [[ANY_OF_RED]], %[[ELSE_1]] ], [ [[SEL]], %[[ELSE_2]] ] 26; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 27; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] 28; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]] 29; CHECK: [[EXIT]]: 30; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[ANY_OF_RED_NEXT]], %[[LOOP_LATCH]] ] 31; CHECK-NEXT: ret i32 [[RES]] 32; 33entry: 34 br label %loop.header 35 36loop.header: 37 %any.of.red = phi i32 [ 0, %entry ], [ %any.of.red.next, %loop.latch ] 38 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 39 br i1 %c.0, label %loop.latch, label %else.1 40 41else.1: 42 br i1 %c.1, label %loop.latch, label %else.2 43 44else.2: 45 %l = load ptr, ptr %src, align 8 46 %c.2 = icmp eq ptr %l, null 47 %sel = select i1 %c.2, i32 0, i32 %any.of.red 48 br label %loop.latch 49 50loop.latch: 51 %any.of.red.next = phi i32 [ %any.of.red, %loop.header ], [ %any.of.red, %else.1 ], [ %sel, %else.2 ] 52 %iv.next = add i64 %iv, 1 53 %ec = icmp eq i64 %iv.next, %N 54 br i1 %ec, label %exit, label %loop.header 55 56exit: 57 %res = phi i32 [ %any.of.red.next, %loop.latch ] 58 ret i32 %res 59} 60 61define i32 @any_of_reduction_used_in_blend_with_multiple_phis(ptr %src, i64 %N, i1 %c.0, i1 %c.1) #0 { 62; CHECK-LABEL: define i32 @any_of_reduction_used_in_blend_with_multiple_phis( 63; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]], i1 [[C_0:%.*]], i1 [[C_1:%.*]]) #[[ATTR0]] { 64; CHECK-NEXT: [[ENTRY:.*]]: 65; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 66; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2 67; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]] 68; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 69; CHECK: [[VECTOR_PH]]: 70; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 71; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 2 72; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]] 73; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 74; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 75; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 76; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C_0]], i64 0 77; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer 78; CHECK-NEXT: [[TMP6:%.*]] = xor <vscale x 2 x i1> [[BROADCAST_SPLAT]], splat (i1 true) 79; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C_1]], i64 0 80; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer 81; CHECK-NEXT: [[TMP7:%.*]] = xor <vscale x 2 x i1> [[BROADCAST_SPLAT2]], splat (i1 true) 82; CHECK-NEXT: [[TMP8:%.*]] = select <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i1> [[TMP7]], <vscale x 2 x i1> zeroinitializer 83; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[SRC]], i64 0 84; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer 85; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 86; CHECK: [[VECTOR_BODY]]: 87; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 88; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PREDPHI:%.*]], %[[VECTOR_BODY]] ] 89; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 2 x ptr> @llvm.masked.gather.nxv2p0.nxv2p0(<vscale x 2 x ptr> [[BROADCAST_SPLAT4]], i32 8, <vscale x 2 x i1> [[TMP8]], <vscale x 2 x ptr> poison) 90; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <vscale x 2 x ptr> [[WIDE_MASKED_GATHER]], zeroinitializer 91; CHECK-NEXT: [[TMP10:%.*]] = or <vscale x 2 x i1> [[VEC_PHI]], [[TMP9]] 92; CHECK-NEXT: [[PREDPHI]] = select <vscale x 2 x i1> [[TMP8]], <vscale x 2 x i1> [[TMP10]], <vscale x 2 x i1> [[VEC_PHI]] 93; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] 94; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 95; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 96; CHECK: [[MIDDLE_BLOCK]]: 97; CHECK-NEXT: [[TMP12:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[PREDPHI]]) 98; CHECK-NEXT: [[TMP13:%.*]] = freeze i1 [[TMP12]] 99; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP13]], i32 0, i32 0 100; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 101; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 102; CHECK: [[SCALAR_PH]]: 103; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 104; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 105; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 106; CHECK: [[LOOP_HEADER]]: 107; CHECK-NEXT: [[ANY_OF_RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ANY_OF_RED_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 108; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH]] ] 109; CHECK-NEXT: br i1 [[C_0]], label %[[X_1:.*]], label %[[ELSE_1:.*]] 110; CHECK: [[ELSE_1]]: 111; CHECK-NEXT: br i1 [[C_1]], label %[[X_1]], label %[[ELSE_2:.*]] 112; CHECK: [[ELSE_2]]: 113; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[SRC]], align 8 114; CHECK-NEXT: [[C_2:%.*]] = icmp eq ptr [[L]], null 115; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C_2]], i32 0, i32 [[ANY_OF_RED]] 116; CHECK-NEXT: br label %[[LOOP_LATCH]] 117; CHECK: [[X_1]]: 118; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[ANY_OF_RED]], %[[LOOP_HEADER]] ], [ [[ANY_OF_RED]], %[[ELSE_1]] ] 119; CHECK-NEXT: br label %[[LOOP_LATCH]] 120; CHECK: [[LOOP_LATCH]]: 121; CHECK-NEXT: [[ANY_OF_RED_NEXT]] = phi i32 [ [[P]], %[[X_1]] ], [ [[SEL]], %[[ELSE_2]] ] 122; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 123; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] 124; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] 125; CHECK: [[EXIT]]: 126; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[ANY_OF_RED_NEXT]], %[[LOOP_LATCH]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 127; CHECK-NEXT: ret i32 [[RES]] 128; 129entry: 130 br label %loop.header 131 132loop.header: 133 %any.of.red = phi i32 [ 0, %entry ], [ %any.of.red.next, %loop.latch ] 134 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 135 br i1 %c.0, label %x.1, label %else.1 136 137else.1: 138 br i1 %c.1, label %x.1, label %else.2 139 140else.2: 141 %l = load ptr, ptr %src, align 8 142 %c.2 = icmp eq ptr %l, null 143 %sel = select i1 %c.2, i32 0, i32 %any.of.red 144 br label %loop.latch 145 146x.1: 147 %p = phi i32 [ %any.of.red, %loop.header ], [ %any.of.red, %else.1 ] 148 br label %loop.latch 149 150loop.latch: 151 %any.of.red.next = phi i32 [ %p, %x.1 ], [ %sel, %else.2 ] 152 %iv.next = add i64 %iv, 1 153 %ec = icmp eq i64 %iv.next, %N 154 br i1 %ec, label %exit, label %loop.header 155 156exit: 157 %res = phi i32 [ %any.of.red.next, %loop.latch ] 158 ret i32 %res 159} 160 161attributes #0 = { "target-cpu"="sifive-p670" } 162;. 163; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 164; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 165; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 166; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 167;. 168