1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s 3; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s 4 5target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6target triple = "arm64-apple-macosx14.0.0" 7 8define void @iv_casts(ptr %dst, ptr %src, i32 %x, i64 %N) #0 { 9; DEFAULT-LABEL: define void @iv_casts( 10; DEFAULT-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 11; DEFAULT-NEXT: entry: 12; DEFAULT-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 13; DEFAULT-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64 14; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 15; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() 16; DEFAULT-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 16 17; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] 18; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 19; DEFAULT: vector.memcheck: 20; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() 21; DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8 22; DEFAULT-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 23; DEFAULT-NEXT: [[TMP6:%.*]] = sub i64 [[DST1]], [[SRC2]] 24; DEFAULT-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]] 25; DEFAULT-NEXT: br i1 [[DIFF_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_PH:%.*]] 26; DEFAULT: vector.ph: 27; DEFAULT-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64() 28; DEFAULT-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 16 29; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP10]] 30; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 31; DEFAULT-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64() 32; DEFAULT-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 16 33; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i32> poison, i32 [[X]], i64 0 34; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 35; DEFAULT-NEXT: [[TMP13:%.*]] = trunc <vscale x 8 x i32> [[BROADCAST_SPLAT]] to <vscale x 8 x i16> 36; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] 37; DEFAULT: vector.body: 38; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 39; DEFAULT-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 0 40; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]] 41; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP20]], i32 0 42; DEFAULT-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64() 43; DEFAULT-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], 8 44; DEFAULT-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP20]], i64 [[TMP24]] 45; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x i8>, ptr [[TMP22]], align 1 46; DEFAULT-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x i8>, ptr [[TMP25]], align 1 47; DEFAULT-NEXT: [[TMP26:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD]] to <vscale x 8 x i16> 48; DEFAULT-NEXT: [[TMP27:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD4]] to <vscale x 8 x i16> 49; DEFAULT-NEXT: [[TMP28:%.*]] = mul <vscale x 8 x i16> [[TMP26]], [[TMP13]] 50; DEFAULT-NEXT: [[TMP29:%.*]] = mul <vscale x 8 x i16> [[TMP27]], [[TMP13]] 51; DEFAULT-NEXT: [[TMP30:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD]] to <vscale x 8 x i16> 52; DEFAULT-NEXT: [[TMP31:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD4]] to <vscale x 8 x i16> 53; DEFAULT-NEXT: [[TMP32:%.*]] = or <vscale x 8 x i16> [[TMP28]], [[TMP30]] 54; DEFAULT-NEXT: [[TMP33:%.*]] = or <vscale x 8 x i16> [[TMP29]], [[TMP31]] 55; DEFAULT-NEXT: [[TMP34:%.*]] = lshr <vscale x 8 x i16> [[TMP32]], trunc (<vscale x 8 x i32> splat (i32 1) to <vscale x 8 x i16>) 56; DEFAULT-NEXT: [[TMP35:%.*]] = lshr <vscale x 8 x i16> [[TMP33]], trunc (<vscale x 8 x i32> splat (i32 1) to <vscale x 8 x i16>) 57; DEFAULT-NEXT: [[TMP36:%.*]] = trunc <vscale x 8 x i16> [[TMP34]] to <vscale x 8 x i8> 58; DEFAULT-NEXT: [[TMP37:%.*]] = trunc <vscale x 8 x i16> [[TMP35]] to <vscale x 8 x i8> 59; DEFAULT-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]] 60; DEFAULT-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[TMP38]], i32 0 61; DEFAULT-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64() 62; DEFAULT-NEXT: [[TMP42:%.*]] = mul i64 [[TMP41]], 8 63; DEFAULT-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr [[TMP38]], i64 [[TMP42]] 64; DEFAULT-NEXT: store <vscale x 8 x i8> [[TMP36]], ptr [[TMP40]], align 1 65; DEFAULT-NEXT: store <vscale x 8 x i8> [[TMP37]], ptr [[TMP43]], align 1 66; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]] 67; DEFAULT-NEXT: [[TMP44:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 68; DEFAULT-NEXT: br i1 [[TMP44]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 69; DEFAULT: middle.block: 70; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 71; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_SCALAR_PH]] 72; DEFAULT: scalar.ph: 73; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ENTRY:%.*]] ] 74; DEFAULT-NEXT: br label [[LOOP:%.*]] 75; DEFAULT: loop: 76; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 77; DEFAULT-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] 78; DEFAULT-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 79; DEFAULT-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32 80; DEFAULT-NEXT: [[MUL16_US:%.*]] = mul i32 [[L_EXT]], [[X]] 81; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 82; DEFAULT-NEXT: [[CONV25_US:%.*]] = zext i8 [[L]] to i32 83; DEFAULT-NEXT: [[ADD34_US:%.*]] = or i32 [[MUL16_US]], [[CONV25_US]] 84; DEFAULT-NEXT: [[SHR35_US:%.*]] = lshr i32 [[ADD34_US]], 1 85; DEFAULT-NEXT: [[CONV36_US:%.*]] = trunc i32 [[SHR35_US]] to i8 86; DEFAULT-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] 87; DEFAULT-NEXT: store i8 [[CONV36_US]], ptr [[GEP_DST]], align 1 88; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] 89; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 90; DEFAULT: exit: 91; DEFAULT-NEXT: ret void 92; 93; PRED-LABEL: define void @iv_casts( 94; PRED-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 95; PRED-NEXT: entry: 96; PRED-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 97; PRED-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64 98; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 99; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 100; PRED: vector.memcheck: 101; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() 102; PRED-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8 103; PRED-NEXT: [[TMP3:%.*]] = sub i64 [[DST1]], [[SRC2]] 104; PRED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]] 105; PRED-NEXT: br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 106; PRED: vector.ph: 107; PRED-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 108; PRED-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 8 109; PRED-NEXT: [[TMP8:%.*]] = sub i64 [[TMP5]], 1 110; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], [[TMP8]] 111; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]] 112; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 113; PRED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64() 114; PRED-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8 115; PRED-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64() 116; PRED-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8 117; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], [[TMP12]] 118; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], [[TMP12]] 119; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 120; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 [[TMP0]]) 121; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i32> poison, i32 [[X]], i64 0 122; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 123; PRED-NEXT: [[TMP16:%.*]] = trunc <vscale x 8 x i32> [[BROADCAST_SPLAT]] to <vscale x 8 x i16> 124; PRED-NEXT: br label [[VECTOR_BODY:%.*]] 125; PRED: vector.body: 126; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 127; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 8 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] 128; PRED-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 0 129; PRED-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP17]] 130; PRED-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP18]], i32 0 131; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0(ptr [[TMP19]], i32 1, <vscale x 8 x i1> [[ACTIVE_LANE_MASK]], <vscale x 8 x i8> poison) 132; PRED-NEXT: [[TMP20:%.*]] = zext <vscale x 8 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 8 x i16> 133; PRED-NEXT: [[TMP21:%.*]] = mul <vscale x 8 x i16> [[TMP20]], [[TMP16]] 134; PRED-NEXT: [[TMP22:%.*]] = zext <vscale x 8 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 8 x i16> 135; PRED-NEXT: [[TMP23:%.*]] = or <vscale x 8 x i16> [[TMP21]], [[TMP22]] 136; PRED-NEXT: [[TMP24:%.*]] = lshr <vscale x 8 x i16> [[TMP23]], trunc (<vscale x 8 x i32> splat (i32 1) to <vscale x 8 x i16>) 137; PRED-NEXT: [[TMP25:%.*]] = trunc <vscale x 8 x i16> [[TMP24]] to <vscale x 8 x i8> 138; PRED-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP17]] 139; PRED-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP26]], i32 0 140; PRED-NEXT: call void @llvm.masked.store.nxv8i8.p0(<vscale x 8 x i8> [[TMP25]], ptr [[TMP27]], i32 1, <vscale x 8 x i1> [[ACTIVE_LANE_MASK]]) 141; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP10]] 142; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 [[INDEX]], i64 [[TMP15]]) 143; PRED-NEXT: [[TMP28:%.*]] = xor <vscale x 8 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true) 144; PRED-NEXT: [[TMP29:%.*]] = extractelement <vscale x 8 x i1> [[TMP28]], i32 0 145; PRED-NEXT: br i1 [[TMP29]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 146; PRED: middle.block: 147; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 148; PRED: scalar.ph: 149; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ENTRY:%.*]] ] 150; PRED-NEXT: br label [[LOOP:%.*]] 151; PRED: loop: 152; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 153; PRED-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] 154; PRED-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 155; PRED-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32 156; PRED-NEXT: [[MUL16_US:%.*]] = mul i32 [[L_EXT]], [[X]] 157; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 158; PRED-NEXT: [[CONV25_US:%.*]] = zext i8 [[L]] to i32 159; PRED-NEXT: [[ADD34_US:%.*]] = or i32 [[MUL16_US]], [[CONV25_US]] 160; PRED-NEXT: [[SHR35_US:%.*]] = lshr i32 [[ADD34_US]], 1 161; PRED-NEXT: [[CONV36_US:%.*]] = trunc i32 [[SHR35_US]] to i8 162; PRED-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] 163; PRED-NEXT: store i8 [[CONV36_US]], ptr [[GEP_DST]], align 1 164; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] 165; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 166; PRED: exit: 167; PRED-NEXT: ret void 168; 169entry: 170 br label %loop 171 172loop: 173 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 174 %gep.src = getelementptr i8, ptr %src, i64 %iv 175 %l = load i8, ptr %gep.src, align 1 176 %l.ext = zext i8 %l to i32 177 %mul = mul i32 %l.ext, %x 178 %iv.next = add i64 %iv, 1 179 %l.ext.2 = zext i8 %l to i32 180 %or = or i32 %mul, %l.ext.2 181 %lshr = lshr i32 %or, 1 182 %trunc = trunc i32 %lshr to i8 183 %gep.dst = getelementptr i8, ptr %dst, i64 %iv 184 store i8 %trunc, ptr %gep.dst, align 1 185 %ec = icmp eq i64 %iv, %N 186 br i1 %ec, label %exit, label %loop 187 188exit: 189 ret void 190} 191 192define void @iv_trunc(i32 %x, ptr %dst, i64 %N) #0 { 193; DEFAULT-LABEL: define void @iv_trunc( 194; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 195; DEFAULT-NEXT: entry: 196; DEFAULT-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1 197; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 198; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 199; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 200; DEFAULT: vector.scevcheck: 201; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] 202; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[MUL_X]], 0 203; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[MUL_X]] 204; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 205; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) 206; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 207; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 208; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] 209; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 210; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false 211; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] 212; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 213; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[MUL_X]], 0 214; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] 215; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] 216; DEFAULT-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 217; DEFAULT: vector.ph: 218; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 219; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 220; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] 221; DEFAULT: vector.body: 222; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 223; DEFAULT-NEXT: [[TMP13:%.*]] = trunc i64 [[INDEX]] to i32 224; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 0 225; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[TMP13]], 1 226; DEFAULT-NEXT: [[TMP16:%.*]] = mul i32 [[MUL_X]], [[TMP14]] 227; DEFAULT-NEXT: [[TMP17:%.*]] = mul i32 [[MUL_X]], [[TMP15]] 228; DEFAULT-NEXT: [[TMP18:%.*]] = zext i32 [[TMP16]] to i64 229; DEFAULT-NEXT: [[TMP19:%.*]] = zext i32 [[TMP17]] to i64 230; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP18]] 231; DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] 232; DEFAULT-NEXT: store i32 1, ptr [[TMP20]], align 4 233; DEFAULT-NEXT: store i32 1, ptr [[TMP21]], align 4 234; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 235; DEFAULT-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 236; DEFAULT-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 237; DEFAULT: middle.block: 238; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 239; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 240; DEFAULT: scalar.ph: 241; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 242; DEFAULT-NEXT: br label [[FOR_BODY:%.*]] 243; DEFAULT: for.body: 244; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] 245; DEFAULT-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32 246; DEFAULT-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]] 247; DEFAULT-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64 248; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]] 249; DEFAULT-NEXT: store i32 1, ptr [[GEP]], align 4 250; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 251; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] 252; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 253; DEFAULT: exit: 254; DEFAULT-NEXT: ret void 255; 256; PRED-LABEL: define void @iv_trunc( 257; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 258; PRED-NEXT: entry: 259; PRED-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1 260; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 261; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 262; PRED: vector.scevcheck: 263; PRED-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] 264; PRED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[MUL_X]], 0 265; PRED-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[MUL_X]] 266; PRED-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 267; PRED-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) 268; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 269; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 270; PRED-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] 271; PRED-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 272; PRED-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false 273; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] 274; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 275; PRED-NEXT: [[TMP10:%.*]] = icmp ne i32 [[MUL_X]], 0 276; PRED-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] 277; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] 278; PRED-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 279; PRED: vector.ph: 280; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 1 281; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2 282; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 283; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], 2 284; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], 2 285; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 286; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 [[TMP0]]) 287; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[MUL_X]], i64 0 288; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer 289; PRED-NEXT: br label [[VECTOR_BODY:%.*]] 290; PRED: vector.body: 291; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ] 292; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] 293; PRED-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] 294; PRED-NEXT: [[TMP16:%.*]] = mul <2 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] 295; PRED-NEXT: [[TMP17:%.*]] = zext <2 x i32> [[TMP16]] to <2 x i64> 296; PRED-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[ACTIVE_LANE_MASK]], i32 0 297; PRED-NEXT: br i1 [[TMP18]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 298; PRED: pred.store.if: 299; PRED-NEXT: [[TMP19:%.*]] = extractelement <2 x i64> [[TMP17]], i32 0 300; PRED-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] 301; PRED-NEXT: store i32 1, ptr [[TMP20]], align 4 302; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] 303; PRED: pred.store.continue: 304; PRED-NEXT: [[TMP21:%.*]] = extractelement <2 x i1> [[ACTIVE_LANE_MASK]], i32 1 305; PRED-NEXT: br i1 [[TMP21]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]] 306; PRED: pred.store.if1: 307; PRED-NEXT: [[TMP22:%.*]] = extractelement <2 x i64> [[TMP17]], i32 1 308; PRED-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP22]] 309; PRED-NEXT: store i32 1, ptr [[TMP23]], align 4 310; PRED-NEXT: br label [[PRED_STORE_CONTINUE2]] 311; PRED: pred.store.continue2: 312; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2 313; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 [[INDEX]], i64 [[TMP15]]) 314; PRED-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true) 315; PRED-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], splat (i32 2) 316; PRED-NEXT: [[TMP25:%.*]] = extractelement <2 x i1> [[TMP24]], i32 0 317; PRED-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 318; PRED: middle.block: 319; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 320; PRED: scalar.ph: 321; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 322; PRED-NEXT: br label [[FOR_BODY:%.*]] 323; PRED: for.body: 324; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] 325; PRED-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32 326; PRED-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]] 327; PRED-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64 328; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]] 329; PRED-NEXT: store i32 1, ptr [[GEP]], align 4 330; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 331; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] 332; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 333; PRED: exit: 334; PRED-NEXT: ret void 335; 336entry: 337 %mul.x = add i32 %x, 1 338 br label %for.body 339 340for.body: ; preds = %for.body, %entry 341 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] 342 %trunc.iv = trunc i64 %iv to i32 343 %add.i = mul i32 %mul.x, %trunc.iv 344 %iv.mul = zext i32 %add.i to i64 345 %gep = getelementptr i32, ptr %dst, i64 %iv.mul 346 store i32 1, ptr %gep, align 4 347 %iv.next = add i64 %iv, 1 348 %ec = icmp eq i64 %iv, %N 349 br i1 %ec, label %exit, label %for.body 350 351exit: 352 ret void 353} 354 355define void @trunc_ivs_and_store(i32 %x, ptr %dst, i64 %N) #0 { 356; 357; DEFAULT-LABEL: define void @trunc_ivs_and_store( 358; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 359; DEFAULT-NEXT: entry: 360; DEFAULT-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[X]] 361; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 362; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 363; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 364; DEFAULT: vector.scevcheck: 365; DEFAULT-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]] 366; DEFAULT-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP1]] 367; DEFAULT-NEXT: [[TMP3:%.*]] = icmp slt i32 [[MUL]], 0 368; DEFAULT-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[MUL]] 369; DEFAULT-NEXT: [[TMP5:%.*]] = trunc i64 [[N]] to i32 370; DEFAULT-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP4]], i32 [[TMP5]]) 371; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0 372; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1 373; DEFAULT-NEXT: [[TMP6:%.*]] = sub i32 0, [[MUL_RESULT]] 374; DEFAULT-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], 0 375; DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false 376; DEFAULT-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]] 377; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[N]], 4294967295 378; DEFAULT-NEXT: [[TMP11:%.*]] = icmp ne i32 [[MUL]], 0 379; DEFAULT-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]] 380; DEFAULT-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]] 381; DEFAULT-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 382; DEFAULT: vector.ph: 383; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 384; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 385; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 386; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] 387; DEFAULT: vector.body: 388; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 389; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 390; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[OFFSET_IDX]], 0 391; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[OFFSET_IDX]], 1 392; DEFAULT-NEXT: [[TMP16:%.*]] = trunc i64 [[INDEX]] to i32 393; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP16]], 0 394; DEFAULT-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], 1 395; DEFAULT-NEXT: [[TMP19:%.*]] = mul i32 [[MUL]], [[TMP17]] 396; DEFAULT-NEXT: [[TMP20:%.*]] = mul i32 [[MUL]], [[TMP18]] 397; DEFAULT-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64 398; DEFAULT-NEXT: [[TMP22:%.*]] = zext i32 [[TMP20]] to i64 399; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]] 400; DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP22]] 401; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[TMP23]], align 4 402; DEFAULT-NEXT: store i32 [[TMP15]], ptr [[TMP24]], align 4 403; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 404; DEFAULT-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 405; DEFAULT-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 406; DEFAULT: middle.block: 407; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 408; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 409; DEFAULT: scalar.ph: 410; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 411; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 412; DEFAULT-NEXT: br label [[LOOP:%.*]] 413; DEFAULT: loop: 414; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 415; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] 416; DEFAULT-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 417; DEFAULT-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[MUL]], [[IV_1_TRUNC]] 418; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 419; DEFAULT-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64 420; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]] 421; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 422; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 423; DEFAULT-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]] 424; DEFAULT-NEXT: br i1 [[EXITCOND_3_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] 425; DEFAULT: exit: 426; DEFAULT-NEXT: ret void 427; 428; PRED-LABEL: define void @trunc_ivs_and_store( 429; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 430; PRED-NEXT: entry: 431; PRED-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[X]] 432; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 433; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 434; PRED: vector.scevcheck: 435; PRED-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]] 436; PRED-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP1]] 437; PRED-NEXT: [[TMP3:%.*]] = icmp slt i32 [[MUL]], 0 438; PRED-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[MUL]] 439; PRED-NEXT: [[TMP5:%.*]] = trunc i64 [[N]] to i32 440; PRED-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP4]], i32 [[TMP5]]) 441; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0 442; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1 443; PRED-NEXT: [[TMP6:%.*]] = sub i32 0, [[MUL_RESULT]] 444; PRED-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], 0 445; PRED-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false 446; PRED-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]] 447; PRED-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[N]], 4294967295 448; PRED-NEXT: [[TMP11:%.*]] = icmp ne i32 [[MUL]], 0 449; PRED-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]] 450; PRED-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]] 451; PRED-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 452; PRED: vector.ph: 453; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3 454; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 455; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 456; PRED-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 457; PRED-NEXT: [[TMP14:%.*]] = sub i64 [[TMP0]], 4 458; PRED-NEXT: [[TMP15:%.*]] = icmp ugt i64 [[TMP0]], 4 459; PRED-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i64 [[TMP14]], i64 0 460; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 [[TMP0]]) 461; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[MUL]], i64 0 462; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 463; PRED-NEXT: br label [[VECTOR_BODY:%.*]] 464; PRED: vector.body: 465; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE7:%.*]] ] 466; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE7]] ] 467; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE7]] ] 468; PRED-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 469; PRED-NEXT: [[TMP17:%.*]] = mul <4 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] 470; PRED-NEXT: [[TMP18:%.*]] = zext <4 x i32> [[TMP17]] to <4 x i64> 471; PRED-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 0 472; PRED-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 473; PRED: pred.store.if: 474; PRED-NEXT: [[TMP20:%.*]] = extractelement <4 x i64> [[TMP18]], i32 0 475; PRED-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]] 476; PRED-NEXT: [[TMP22:%.*]] = add i32 [[OFFSET_IDX]], 0 477; PRED-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4 478; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] 479; PRED: pred.store.continue: 480; PRED-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 1 481; PRED-NEXT: br i1 [[TMP23]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3:%.*]] 482; PRED: pred.store.if2: 483; PRED-NEXT: [[TMP24:%.*]] = extractelement <4 x i64> [[TMP18]], i32 1 484; PRED-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP24]] 485; PRED-NEXT: [[TMP26:%.*]] = add i32 [[OFFSET_IDX]], 1 486; PRED-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4 487; PRED-NEXT: br label [[PRED_STORE_CONTINUE3]] 488; PRED: pred.store.continue3: 489; PRED-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 2 490; PRED-NEXT: br i1 [[TMP27]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]] 491; PRED: pred.store.if4: 492; PRED-NEXT: [[TMP28:%.*]] = extractelement <4 x i64> [[TMP18]], i32 2 493; PRED-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP28]] 494; PRED-NEXT: [[TMP30:%.*]] = add i32 [[OFFSET_IDX]], 2 495; PRED-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 4 496; PRED-NEXT: br label [[PRED_STORE_CONTINUE5]] 497; PRED: pred.store.continue5: 498; PRED-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 3 499; PRED-NEXT: br i1 [[TMP31]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7]] 500; PRED: pred.store.if6: 501; PRED-NEXT: [[TMP32:%.*]] = extractelement <4 x i64> [[TMP18]], i32 3 502; PRED-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP32]] 503; PRED-NEXT: [[TMP34:%.*]] = add i32 [[OFFSET_IDX]], 3 504; PRED-NEXT: store i32 [[TMP34]], ptr [[TMP33]], align 4 505; PRED-NEXT: br label [[PRED_STORE_CONTINUE7]] 506; PRED: pred.store.continue7: 507; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 508; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[INDEX]], i64 [[TMP16]]) 509; PRED-NEXT: [[TMP35:%.*]] = xor <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true) 510; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) 511; PRED-NEXT: [[TMP36:%.*]] = extractelement <4 x i1> [[TMP35]], i32 0 512; PRED-NEXT: br i1 [[TMP36]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 513; PRED: middle.block: 514; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 515; PRED: scalar.ph: 516; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 517; PRED-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 518; PRED-NEXT: br label [[LOOP:%.*]] 519; PRED: loop: 520; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 521; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL8]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] 522; PRED-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 523; PRED-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[MUL]], [[IV_1_TRUNC]] 524; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 525; PRED-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64 526; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]] 527; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 528; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 529; PRED-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]] 530; PRED-NEXT: br i1 [[EXITCOND_3_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] 531; PRED: exit: 532; PRED-NEXT: ret void 533; 534entry: 535 %mul = mul i32 %x, %x 536 br label %loop 537 538loop: 539 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ] 540 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] 541 %iv.1.trunc = trunc i64 %iv.1 to i32 542 %iv.1.mul = mul i32 %mul, %iv.1.trunc 543 %iv.2.next = add i32 %iv.2, 1 544 %mul.ext = zext i32 %iv.1.mul to i64 545 %gep = getelementptr i32, ptr %dst, i64 %mul.ext 546 store i32 %iv.2, ptr %gep, align 4 547 %iv.1.next = add i64 %iv.1, 1 548 %exitcond.3.not = icmp eq i64 %iv.1, %N 549 br i1 %exitcond.3.not, label %exit, label %loop 550 551exit: 552 ret void 553} 554 555define void @ivs_trunc_and_ext(i32 %x, ptr %dst, i64 %N) #0 { 556; DEFAULT-LABEL: define void @ivs_trunc_and_ext( 557; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 558; DEFAULT-NEXT: entry: 559; DEFAULT-NEXT: [[ADD:%.*]] = add i32 [[X]], 1 560; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 561; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 562; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 563; DEFAULT: vector.scevcheck: 564; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] 565; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[ADD]], 0 566; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[ADD]] 567; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 568; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) 569; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 570; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 571; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] 572; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 573; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false 574; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] 575; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 576; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[ADD]], 0 577; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] 578; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] 579; DEFAULT-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 580; DEFAULT: vector.ph: 581; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 582; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 583; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 584; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] 585; DEFAULT: vector.body: 586; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 587; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 588; DEFAULT-NEXT: [[TMP13:%.*]] = add i32 [[OFFSET_IDX]], 0 589; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[OFFSET_IDX]], 1 590; DEFAULT-NEXT: [[TMP15:%.*]] = trunc i64 [[INDEX]] to i32 591; DEFAULT-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], 0 592; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP15]], 1 593; DEFAULT-NEXT: [[TMP18:%.*]] = mul i32 [[ADD]], [[TMP16]] 594; DEFAULT-NEXT: [[TMP19:%.*]] = mul i32 [[ADD]], [[TMP17]] 595; DEFAULT-NEXT: [[TMP20:%.*]] = zext i32 [[TMP18]] to i64 596; DEFAULT-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64 597; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]] 598; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]] 599; DEFAULT-NEXT: store i32 [[TMP13]], ptr [[TMP22]], align 4 600; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[TMP23]], align 4 601; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 602; DEFAULT-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 603; DEFAULT-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 604; DEFAULT: middle.block: 605; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 606; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 607; DEFAULT: scalar.ph: 608; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 609; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 610; DEFAULT-NEXT: br label [[LOOP:%.*]] 611; DEFAULT: loop: 612; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 613; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] 614; DEFAULT-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 615; DEFAULT-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]] 616; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 617; DEFAULT-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64 618; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]] 619; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 620; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 621; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]] 622; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] 623; DEFAULT: exit: 624; DEFAULT-NEXT: ret void 625; 626; PRED-LABEL: define void @ivs_trunc_and_ext( 627; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { 628; PRED-NEXT: entry: 629; PRED-NEXT: [[ADD:%.*]] = add i32 [[X]], 1 630; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 631; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 632; PRED: vector.scevcheck: 633; PRED-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] 634; PRED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[ADD]], 0 635; PRED-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[ADD]] 636; PRED-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 637; PRED-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) 638; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 639; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 640; PRED-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] 641; PRED-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 642; PRED-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false 643; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] 644; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 645; PRED-NEXT: [[TMP10:%.*]] = icmp ne i32 [[ADD]], 0 646; PRED-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] 647; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] 648; PRED-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 649; PRED: vector.ph: 650; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3 651; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 652; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 653; PRED-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 654; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], 4 655; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], 4 656; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 657; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 [[TMP0]]) 658; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[ADD]], i64 0 659; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 660; PRED-NEXT: br label [[VECTOR_BODY:%.*]] 661; PRED: vector.body: 662; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] 663; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ] 664; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ] 665; PRED-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 666; PRED-NEXT: [[TMP16:%.*]] = mul <4 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] 667; PRED-NEXT: [[TMP17:%.*]] = zext <4 x i32> [[TMP16]] to <4 x i64> 668; PRED-NEXT: [[TMP18:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 0 669; PRED-NEXT: br i1 [[TMP18]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 670; PRED: pred.store.if: 671; PRED-NEXT: [[TMP19:%.*]] = extractelement <4 x i64> [[TMP17]], i32 0 672; PRED-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] 673; PRED-NEXT: [[TMP21:%.*]] = add i32 [[OFFSET_IDX]], 0 674; PRED-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4 675; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] 676; PRED: pred.store.continue: 677; PRED-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 1 678; PRED-NEXT: br i1 [[TMP22]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] 679; PRED: pred.store.if1: 680; PRED-NEXT: [[TMP23:%.*]] = extractelement <4 x i64> [[TMP17]], i32 1 681; PRED-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP23]] 682; PRED-NEXT: [[TMP25:%.*]] = add i32 [[OFFSET_IDX]], 1 683; PRED-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4 684; PRED-NEXT: br label [[PRED_STORE_CONTINUE2]] 685; PRED: pred.store.continue2: 686; PRED-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 2 687; PRED-NEXT: br i1 [[TMP26]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] 688; PRED: pred.store.if3: 689; PRED-NEXT: [[TMP27:%.*]] = extractelement <4 x i64> [[TMP17]], i32 2 690; PRED-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP27]] 691; PRED-NEXT: [[TMP29:%.*]] = add i32 [[OFFSET_IDX]], 2 692; PRED-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 693; PRED-NEXT: br label [[PRED_STORE_CONTINUE4]] 694; PRED: pred.store.continue4: 695; PRED-NEXT: [[TMP30:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 3 696; PRED-NEXT: br i1 [[TMP30]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] 697; PRED: pred.store.if5: 698; PRED-NEXT: [[TMP31:%.*]] = extractelement <4 x i64> [[TMP17]], i32 3 699; PRED-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP31]] 700; PRED-NEXT: [[TMP33:%.*]] = add i32 [[OFFSET_IDX]], 3 701; PRED-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4 702; PRED-NEXT: br label [[PRED_STORE_CONTINUE6]] 703; PRED: pred.store.continue6: 704; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 705; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[INDEX]], i64 [[TMP15]]) 706; PRED-NEXT: [[TMP34:%.*]] = xor <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true) 707; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) 708; PRED-NEXT: [[TMP35:%.*]] = extractelement <4 x i1> [[TMP34]], i32 0 709; PRED-NEXT: br i1 [[TMP35]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 710; PRED: middle.block: 711; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 712; PRED: scalar.ph: 713; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 714; PRED-NEXT: [[BC_RESUME_VAL7:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 715; PRED-NEXT: br label [[LOOP:%.*]] 716; PRED: loop: 717; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 718; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL7]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] 719; PRED-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 720; PRED-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]] 721; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 722; PRED-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64 723; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]] 724; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 725; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 726; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]] 727; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] 728; PRED: exit: 729; PRED-NEXT: ret void 730; 731 732entry: 733 %add = add i32 %x, 1 734 br label %loop 735 736loop: 737 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ] 738 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] 739 %iv.trunc = trunc i64 %iv.1 to i32 740 %iv.mul = mul i32 %add, %iv.trunc 741 %iv.2.next = add i32 %iv.2, 1 742 %ext = zext i32 %iv.mul to i64 743 %gep = getelementptr i32, ptr %dst, i64 %ext 744 store i32 %iv.2, ptr %gep, align 4 745 %iv.1.next = add i64 %iv.1, 1 746 %ec = icmp eq i64 %iv.1, %N 747 br i1 %ec, label %exit, label %loop 748 749exit: 750 ret void 751} 752 753define void @exit_cond_zext_iv(ptr %dst, i64 %N) { 754; DEFAULT-LABEL: define void @exit_cond_zext_iv( 755; DEFAULT-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { 756; DEFAULT-NEXT: entry: 757; DEFAULT-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) 758; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2 759; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 760; DEFAULT: vector.scevcheck: 761; DEFAULT-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) 762; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 763; DEFAULT-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32 764; DEFAULT-NEXT: [[TMP3:%.*]] = add i32 1, [[TMP2]] 765; DEFAULT-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 766; DEFAULT-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 767; DEFAULT-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] 768; DEFAULT-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 769; DEFAULT: vector.ph: 770; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2 771; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] 772; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 773; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] 774; DEFAULT: vector.body: 775; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 776; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 0 777; DEFAULT-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 778; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP7]], i32 2 779; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP8]], i32 2 780; DEFAULT-NEXT: store i32 0, ptr [[TMP9]], align 8 781; DEFAULT-NEXT: store i32 0, ptr [[TMP10]], align 8 782; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 783; DEFAULT-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 784; DEFAULT-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 785; DEFAULT: middle.block: 786; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] 787; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 788; DEFAULT: scalar.ph: 789; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 790; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 791; DEFAULT-NEXT: br label [[LOOP:%.*]] 792; DEFAULT: loop: 793; DEFAULT-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 794; DEFAULT-NEXT: [[IV_CONV:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_EXT:%.*]], [[LOOP]] ] 795; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2 796; DEFAULT-NEXT: store i32 0, ptr [[GEP]], align 8 797; DEFAULT-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 798; DEFAULT-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64 799; DEFAULT-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]] 800; DEFAULT-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP11:![0-9]+]] 801; DEFAULT: exit: 802; DEFAULT-NEXT: ret void 803; 804; PRED-LABEL: define void @exit_cond_zext_iv( 805; PRED-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { 806; PRED-NEXT: entry: 807; PRED-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) 808; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 809; PRED: vector.scevcheck: 810; PRED-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) 811; PRED-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 812; PRED-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32 813; PRED-NEXT: [[TMP3:%.*]] = add i32 1, [[TMP2]] 814; PRED-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 815; PRED-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 816; PRED-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] 817; PRED-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 818; PRED: vector.ph: 819; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX1]], 1 820; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2 821; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 822; PRED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX1]], 1 823; PRED-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 824; PRED-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 825; PRED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT2]], <2 x i64> poison, <2 x i32> zeroinitializer 826; PRED-NEXT: br label [[VECTOR_BODY:%.*]] 827; PRED: vector.body: 828; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE5:%.*]] ] 829; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[INDEX]], i64 0 830; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer 831; PRED-NEXT: [[VEC_IV:%.*]] = add <2 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1> 832; PRED-NEXT: [[TMP7:%.*]] = icmp ule <2 x i64> [[VEC_IV]], [[BROADCAST_SPLAT3]] 833; PRED-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0 834; PRED-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 835; PRED: pred.store.if: 836; PRED-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0 837; PRED-NEXT: [[TMP10:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP9]], i32 2 838; PRED-NEXT: store i32 0, ptr [[TMP10]], align 8 839; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] 840; PRED: pred.store.continue: 841; PRED-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1 842; PRED-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5]] 843; PRED: pred.store.if4: 844; PRED-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 1 845; PRED-NEXT: [[TMP13:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP12]], i32 2 846; PRED-NEXT: store i32 0, ptr [[TMP13]], align 8 847; PRED-NEXT: br label [[PRED_STORE_CONTINUE5]] 848; PRED: pred.store.continue5: 849; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2 850; PRED-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 851; PRED-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 852; PRED: middle.block: 853; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 854; PRED: scalar.ph: 855; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 856; PRED-NEXT: [[BC_RESUME_VAL6:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 857; PRED-NEXT: br label [[LOOP:%.*]] 858; PRED: loop: 859; PRED-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] 860; PRED-NEXT: [[IV_CONV:%.*]] = phi i64 [ [[BC_RESUME_VAL6]], [[SCALAR_PH]] ], [ [[IV_EXT:%.*]], [[LOOP]] ] 861; PRED-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2 862; PRED-NEXT: store i32 0, ptr [[GEP]], align 8 863; PRED-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 864; PRED-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64 865; PRED-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]] 866; PRED-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP11:![0-9]+]] 867; PRED: exit: 868; PRED-NEXT: ret void 869; 870entry: 871 br label %loop 872 873loop: 874 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ] 875 %iv.conv = phi i64 [ 0, %entry ], [ %iv.ext, %loop ] 876 %gep = getelementptr {[100 x i32], i32, i32}, ptr %dst, i64 %iv.conv, i32 2 877 store i32 0, ptr %gep, align 8 878 %iv.1.next = add i32 %iv.1, 1 879 %iv.ext = zext i32 %iv.1.next to i64 880 %c = icmp ult i64 %iv.ext, %N 881 br i1 %c, label %loop, label %exit 882 883exit: 884 ret void 885} 886 887attributes #0 = { "target-features"="+sve" } 888 889;. 890; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 891; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 892; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 893; DEFAULT: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} 894; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 895; DEFAULT: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} 896; DEFAULT: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 897; DEFAULT: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} 898; DEFAULT: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 899; DEFAULT: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} 900; DEFAULT: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 901; DEFAULT: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]} 902;. 903; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 904; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 905; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 906; PRED: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} 907; PRED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 908; PRED: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} 909; PRED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 910; PRED: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} 911; PRED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 912; PRED: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} 913; PRED: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 914; PRED: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]} 915;. 916