xref: /llvm-project/llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll (revision 3ff1d0198575282ad585c891b2e61e904a7d8c5a) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2; RUN: opt -p loop-vectorize -mtriple aarch64 -mcpu=neoverse-v1 -S %s | FileCheck %s
3
4; Test case for https://github.com/llvm/llvm-project/issues/94328.
5define void @sdiv_feeding_gep(ptr %dst, i32 %x, i64 %M, i64 %conv6, i64 %N) {
6; CHECK-LABEL: define void @sdiv_feeding_gep(
7; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i64 [[M:%.*]], i64 [[CONV6:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8; CHECK-NEXT:  [[ENTRY:.*]]:
9; CHECK-NEXT:    [[CONV61:%.*]] = zext i32 [[X]] to i64
10; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
11; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[TMP0]], 4
12; CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 8, i64 [[TMP1]])
13; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]
14; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
15; CHECK:       [[VECTOR_SCEVCHECK]]:
16; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[N]], -1
17; CHECK-NEXT:    [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
18; CHECK-NEXT:    [[TMP5:%.*]] = icmp slt i32 [[TMP4]], 0
19; CHECK-NEXT:    [[TMP6:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
20; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
21; CHECK-NEXT:    br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
22; CHECK:       [[VECTOR_PH]]:
23; CHECK-NEXT:    [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
24; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP8]], 4
25; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP9]]
26; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
27; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
28; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP10]], 4
29; CHECK-NEXT:    [[TMP18:%.*]] = sdiv i64 [[M]], [[CONV6]]
30; CHECK-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP18]] to i32
31; CHECK-NEXT:    [[TMP22:%.*]] = mul i64 [[TMP18]], [[CONV61]]
32; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[X]], [[TMP20]]
33; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
34; CHECK:       [[VECTOR_BODY]]:
35; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
36; CHECK-NEXT:    [[TMP12:%.*]] = add i64 [[INDEX]], 0
37; CHECK-NEXT:    [[TMP24:%.*]] = sub i64 [[TMP12]], [[TMP22]]
38; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[TMP24]] to i32
39; CHECK-NEXT:    [[TMP30:%.*]] = add i32 [[TMP28]], [[TMP26]]
40; CHECK-NEXT:    [[TMP32:%.*]] = sext i32 [[TMP30]] to i64
41; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP32]]
42; CHECK-NEXT:    [[TMP36:%.*]] = getelementptr double, ptr [[TMP34]], i32 0
43; CHECK-NEXT:    [[TMP37:%.*]] = call i64 @llvm.vscale.i64()
44; CHECK-NEXT:    [[TMP38:%.*]] = mul i64 [[TMP37]], 2
45; CHECK-NEXT:    [[TMP39:%.*]] = getelementptr double, ptr [[TMP34]], i64 [[TMP38]]
46; CHECK-NEXT:    store <vscale x 2 x double> zeroinitializer, ptr [[TMP36]], align 8
47; CHECK-NEXT:    store <vscale x 2 x double> zeroinitializer, ptr [[TMP39]], align 8
48; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP11]]
49; CHECK-NEXT:    [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
50; CHECK-NEXT:    br i1 [[TMP40]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
51; CHECK:       [[MIDDLE_BLOCK]]:
52; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
53; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
54; CHECK:       [[SCALAR_PH]]:
55; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
56; CHECK-NEXT:    br label %[[LOOP:.*]]
57; CHECK:       [[LOOP]]:
58; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
59; CHECK-NEXT:    [[DIV18:%.*]] = sdiv i64 [[M]], [[CONV6]]
60; CHECK-NEXT:    [[CONV20:%.*]] = trunc i64 [[DIV18]] to i32
61; CHECK-NEXT:    [[MUL30:%.*]] = mul i64 [[DIV18]], [[CONV61]]
62; CHECK-NEXT:    [[SUB31:%.*]] = sub i64 [[IV]], [[MUL30]]
63; CHECK-NEXT:    [[CONV34:%.*]] = trunc i64 [[SUB31]] to i32
64; CHECK-NEXT:    [[MUL35:%.*]] = mul i32 [[X]], [[CONV20]]
65; CHECK-NEXT:    [[ADD36:%.*]] = add i32 [[MUL35]], [[CONV34]]
66; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[ADD36]] to i64
67; CHECK-NEXT:    [[GEP:%.*]] = getelementptr double, ptr [[DST]], i64 [[IDXPROM]]
68; CHECK-NEXT:    store double 0.000000e+00, ptr [[GEP]], align 8
69; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
70; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
71; CHECK-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
72; CHECK:       [[EXIT]]:
73; CHECK-NEXT:    ret void
74;
75entry:
76  %conv61 = zext i32 %x to i64
77  br label %loop
78
79loop:
80  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
81  %div18 = sdiv i64 %M, %conv6
82  %conv20 = trunc i64 %div18 to i32
83  %mul30 = mul i64 %div18, %conv61
84  %sub31 = sub i64 %iv, %mul30
85  %conv34 = trunc i64 %sub31 to i32
86  %mul35 = mul i32 %x, %conv20
87  %add36 = add i32 %mul35, %conv34
88  %idxprom = sext i32 %add36 to i64
89  %gep = getelementptr double, ptr %dst, i64 %idxprom
90  store double 0.000000e+00, ptr %gep, align 8
91  %iv.next = add i64 %iv, 1
92  %ec = icmp eq i64 %iv.next, %N
93  br i1 %ec, label %exit, label %loop
94
95exit:
96  ret void
97}
98
99define void @sdiv_feeding_gep_predicated(ptr %dst, i32 %x, i64 %M, i64 %conv6, i64 %N) {
100; CHECK-LABEL: define void @sdiv_feeding_gep_predicated(
101; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i64 [[M:%.*]], i64 [[CONV6:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
102; CHECK-NEXT:  [[ENTRY:.*]]:
103; CHECK-NEXT:    [[CONV61:%.*]] = zext i32 [[X]] to i64
104; CHECK-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
105; CHECK:       [[VECTOR_SCEVCHECK]]:
106; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
107; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
108; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
109; CHECK-NEXT:    [[TMP3:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
110; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]
111; CHECK-NEXT:    br i1 [[TMP4]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
112; CHECK:       [[VECTOR_PH]]:
113; CHECK-NEXT:    [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
114; CHECK-NEXT:    [[TMP6:%.*]] = mul i64 [[TMP5]], 2
115; CHECK-NEXT:    [[TMP7:%.*]] = sub i64 [[TMP6]], 1
116; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i64 [[N]], [[TMP7]]
117; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP6]]
118; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
119; CHECK-NEXT:    [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
120; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP8]], 2
121; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
122; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP10]], 2
123; CHECK-NEXT:    [[TMP12:%.*]] = sub i64 [[N]], [[TMP11]]
124; CHECK-NEXT:    [[TMP13:%.*]] = icmp ugt i64 [[N]], [[TMP11]]
125; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP12]], i64 0
126; CHECK-NEXT:    [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 [[N]])
127; CHECK-NEXT:    [[TMP15:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
128; CHECK-NEXT:    [[TMP17:%.*]] = mul <vscale x 2 x i64> [[TMP15]], splat (i64 1)
129; CHECK-NEXT:    [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP17]]
130; CHECK-NEXT:    [[TMP20:%.*]] = mul i64 1, [[TMP9]]
131; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP20]], i64 0
132; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
133; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[M]], i64 0
134; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
135; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
136; CHECK:       [[VECTOR_BODY]]:
137; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
138; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
139; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
140; CHECK-NEXT:    [[TMP21:%.*]] = add i64 [[INDEX]], 0
141; CHECK-NEXT:    [[TMP22:%.*]] = icmp ule <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
142; CHECK-NEXT:    [[TMP23:%.*]] = select <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i1> [[TMP22]], <vscale x 2 x i1> zeroinitializer
143; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <vscale x 2 x i1> [[TMP23]], i32 0
144; CHECK-NEXT:    [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[CONV6]], i64 1
145; CHECK-NEXT:    [[TMP26:%.*]] = sdiv i64 [[M]], [[TMP25]]
146; CHECK-NEXT:    [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32
147; CHECK-NEXT:    [[TMP28:%.*]] = mul i64 [[TMP26]], [[CONV61]]
148; CHECK-NEXT:    [[TMP29:%.*]] = sub i64 [[TMP21]], [[TMP28]]
149; CHECK-NEXT:    [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32
150; CHECK-NEXT:    [[TMP31:%.*]] = mul i32 [[X]], [[TMP27]]
151; CHECK-NEXT:    [[TMP32:%.*]] = add i32 [[TMP31]], [[TMP30]]
152; CHECK-NEXT:    [[TMP33:%.*]] = sext i32 [[TMP32]] to i64
153; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP33]]
154; CHECK-NEXT:    [[TMP35:%.*]] = getelementptr double, ptr [[TMP34]], i32 0
155; CHECK-NEXT:    call void @llvm.masked.store.nxv2f64.p0(<vscale x 2 x double> zeroinitializer, ptr [[TMP35]], i32 8, <vscale x 2 x i1> [[TMP23]])
156; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP9]]
157; CHECK-NEXT:    [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX]], i64 [[TMP14]])
158; CHECK-NEXT:    [[TMP36:%.*]] = xor <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true)
159; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[DOTSPLAT]]
160; CHECK-NEXT:    [[TMP37:%.*]] = extractelement <vscale x 2 x i1> [[TMP36]], i32 0
161; CHECK-NEXT:    br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
162; CHECK:       [[MIDDLE_BLOCK]]:
163; CHECK-NEXT:    br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
164; CHECK:       [[SCALAR_PH]]:
165; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
166; CHECK-NEXT:    br label %[[LOOP:.*]]
167; CHECK:       [[LOOP]]:
168; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
169; CHECK-NEXT:    [[C:%.*]] = icmp ule i64 [[IV]], [[M]]
170; CHECK-NEXT:    br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
171; CHECK:       [[THEN]]:
172; CHECK-NEXT:    [[DIV18:%.*]] = sdiv i64 [[M]], [[CONV6]]
173; CHECK-NEXT:    [[CONV20:%.*]] = trunc i64 [[DIV18]] to i32
174; CHECK-NEXT:    [[MUL30:%.*]] = mul i64 [[DIV18]], [[CONV61]]
175; CHECK-NEXT:    [[SUB31:%.*]] = sub i64 [[IV]], [[MUL30]]
176; CHECK-NEXT:    [[CONV34:%.*]] = trunc i64 [[SUB31]] to i32
177; CHECK-NEXT:    [[MUL35:%.*]] = mul i32 [[X]], [[CONV20]]
178; CHECK-NEXT:    [[ADD36:%.*]] = add i32 [[MUL35]], [[CONV34]]
179; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[ADD36]] to i64
180; CHECK-NEXT:    [[GEP:%.*]] = getelementptr double, ptr [[DST]], i64 [[IDXPROM]]
181; CHECK-NEXT:    store double 0.000000e+00, ptr [[GEP]], align 8
182; CHECK-NEXT:    br label %[[LOOP_LATCH]]
183; CHECK:       [[LOOP_LATCH]]:
184; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
185; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
186; CHECK-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
187; CHECK:       [[EXIT]]:
188; CHECK-NEXT:    ret void
189;
190entry:
191  %conv61 = zext i32 %x to i64
192  br label %loop
193
194loop:
195  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
196  %c = icmp ule i64 %iv, %M
197  br i1 %c, label %then, label %loop.latch
198
199then:
200  %div18 = sdiv i64 %M, %conv6
201  %conv20 = trunc i64 %div18 to i32
202  %mul30 = mul i64 %div18, %conv61
203  %sub31 = sub i64 %iv, %mul30
204  %conv34 = trunc i64 %sub31 to i32
205  %mul35 = mul i32 %x, %conv20
206  %add36 = add i32 %mul35, %conv34
207  %idxprom = sext i32 %add36 to i64
208  %gep = getelementptr double, ptr %dst, i64 %idxprom
209  store double 0.000000e+00, ptr %gep, align 8
210  br label %loop.latch
211
212loop.latch:
213  %iv.next = add i64 %iv, 1
214  %ec = icmp eq i64 %iv.next, %N
215  br i1 %ec, label %exit, label %loop
216
217exit:
218  ret void
219}
220
221; Test case for https://github.com/llvm/llvm-project/issues/80416.
222define void @udiv_urem_feeding_gep(i64 %x, ptr %dst, i64 %N) {
223; CHECK-LABEL: define void @udiv_urem_feeding_gep(
224; CHECK-SAME: i64 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
225; CHECK-NEXT:  [[ENTRY:.*]]:
226; CHECK-NEXT:    [[MUL_1_I:%.*]] = mul i64 [[X]], [[X]]
227; CHECK-NEXT:    [[MUL_2_I:%.*]] = mul i64 [[MUL_1_I]], [[X]]
228; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[N]], 1
229; CHECK-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
230; CHECK:       [[VECTOR_SCEVCHECK]]:
231; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[N]] to i32
232; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
233; CHECK-NEXT:    [[TMP3:%.*]] = icmp ugt i64 [[N]], 4294967295
234; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]
235; CHECK-NEXT:    br i1 [[TMP4]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
236; CHECK:       [[VECTOR_PH]]:
237; CHECK-NEXT:    [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
238; CHECK-NEXT:    [[TMP6:%.*]] = mul i64 [[TMP5]], 2
239; CHECK-NEXT:    [[TMP7:%.*]] = sub i64 [[TMP6]], 1
240; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i64 [[TMP0]], [[TMP7]]
241; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP6]]
242; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
243; CHECK-NEXT:    [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
244; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP8]], 2
245; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
246; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[TMP10]], 2
247; CHECK-NEXT:    [[TMP12:%.*]] = sub i64 [[TMP0]], [[TMP11]]
248; CHECK-NEXT:    [[TMP13:%.*]] = icmp ugt i64 [[TMP0]], [[TMP11]]
249; CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP12]], i64 0
250; CHECK-NEXT:    [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 [[TMP0]])
251; CHECK-NEXT:    [[TMP15:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
252; CHECK-NEXT:    [[TMP17:%.*]] = mul <vscale x 2 x i64> [[TMP15]], splat (i64 1)
253; CHECK-NEXT:    [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP17]]
254; CHECK-NEXT:    [[TMP20:%.*]] = mul i64 1, [[TMP9]]
255; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP20]], i64 0
256; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
257; CHECK-NEXT:    [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[MUL_2_I]], i64 0
258; CHECK-NEXT:    [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
259; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
260; CHECK:       [[VECTOR_BODY]]:
261; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
262; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
263; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
264; CHECK-NEXT:    [[TMP21:%.*]] = add i64 [[INDEX]], 0
265; CHECK-NEXT:    [[TMP23:%.*]] = udiv <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT4]]
266; CHECK-NEXT:    [[TMP24:%.*]] = urem i64 [[TMP21]], [[MUL_2_I]]
267; CHECK-NEXT:    [[TMP25:%.*]] = udiv i64 [[TMP24]], [[MUL_1_I]]
268; CHECK-NEXT:    [[TMP26:%.*]] = urem i64 [[TMP24]], [[MUL_1_I]]
269; CHECK-NEXT:    [[TMP27:%.*]] = udiv i64 [[TMP26]], [[X]]
270; CHECK-NEXT:    [[TMP28:%.*]] = urem i64 [[TMP26]], [[X]]
271; CHECK-NEXT:    [[TMP29:%.*]] = extractelement <vscale x 2 x i64> [[TMP23]], i32 0
272; CHECK-NEXT:    [[TMP30:%.*]] = mul i64 [[X]], [[TMP29]]
273; CHECK-NEXT:    [[TMP31:%.*]] = add i64 [[TMP30]], [[TMP25]]
274; CHECK-NEXT:    [[TMP32:%.*]] = mul i64 [[TMP31]], [[X]]
275; CHECK-NEXT:    [[TMP33:%.*]] = add i64 [[TMP32]], [[TMP27]]
276; CHECK-NEXT:    [[TMP34:%.*]] = mul i64 [[TMP33]], [[X]]
277; CHECK-NEXT:    [[TMP35:%.*]] = add i64 [[TMP34]], [[TMP28]]
278; CHECK-NEXT:    [[TMP36:%.*]] = shl i64 [[TMP35]], 32
279; CHECK-NEXT:    [[TMP37:%.*]] = ashr i64 [[TMP36]], 32
280; CHECK-NEXT:    [[TMP38:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP37]]
281; CHECK-NEXT:    [[TMP39:%.*]] = getelementptr i64, ptr [[TMP38]], i32 0
282; CHECK-NEXT:    call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP23]], ptr [[TMP39]], i32 4, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])
283; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP9]]
284; CHECK-NEXT:    [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX]], i64 [[TMP14]])
285; CHECK-NEXT:    [[TMP47:%.*]] = xor <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true)
286; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
287; CHECK-NEXT:    [[TMP48:%.*]] = extractelement <vscale x 2 x i1> [[TMP47]], i32 0
288; CHECK-NEXT:    br i1 [[TMP48]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
289; CHECK:       [[MIDDLE_BLOCK]]:
290; CHECK-NEXT:    br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
291; CHECK:       [[SCALAR_PH]]:
292; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
293; CHECK-NEXT:    br label %[[LOOP:.*]]
294; CHECK:       [[LOOP]]:
295; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
296; CHECK-NEXT:    [[DIV_I:%.*]] = udiv i64 [[IV]], [[MUL_2_I]]
297; CHECK-NEXT:    [[REM_I:%.*]] = urem i64 [[IV]], [[MUL_2_I]]
298; CHECK-NEXT:    [[DIV_1_I:%.*]] = udiv i64 [[REM_I]], [[MUL_1_I]]
299; CHECK-NEXT:    [[REM_1_I:%.*]] = urem i64 [[REM_I]], [[MUL_1_I]]
300; CHECK-NEXT:    [[DIV_2_I:%.*]] = udiv i64 [[REM_1_I]], [[X]]
301; CHECK-NEXT:    [[REM_2_I:%.*]] = urem i64 [[REM_1_I]], [[X]]
302; CHECK-NEXT:    [[MUL_I:%.*]] = mul i64 [[X]], [[DIV_I]]
303; CHECK-NEXT:    [[ADD_I:%.*]] = add i64 [[MUL_I]], [[DIV_1_I]]
304; CHECK-NEXT:    [[MUL_1_I9:%.*]] = mul i64 [[ADD_I]], [[X]]
305; CHECK-NEXT:    [[ADD_1_I:%.*]] = add i64 [[MUL_1_I9]], [[DIV_2_I]]
306; CHECK-NEXT:    [[MUL_2_I11:%.*]] = mul i64 [[ADD_1_I]], [[X]]
307; CHECK-NEXT:    [[ADD_2_I:%.*]] = add i64 [[MUL_2_I11]], [[REM_2_I]]
308; CHECK-NEXT:    [[SEXT_I:%.*]] = shl i64 [[ADD_2_I]], 32
309; CHECK-NEXT:    [[CONV6_I:%.*]] = ashr i64 [[SEXT_I]], 32
310; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i64, ptr [[DST]], i64 [[CONV6_I]]
311; CHECK-NEXT:    store i64 [[DIV_I]], ptr [[GEP]], align 4
312; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
313; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[N]]
314; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
315; CHECK:       [[EXIT]]:
316; CHECK-NEXT:    ret void
317;
318entry:
319  %mul.1.i = mul i64 %x, %x
320  %mul.2.i = mul i64 %mul.1.i, %x
321  br label %loop
322
323loop:
324  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
325  %div.i = udiv i64 %iv, %mul.2.i
326  %rem.i = urem i64 %iv, %mul.2.i
327  %div.1.i = udiv i64 %rem.i, %mul.1.i
328  %rem.1.i = urem i64 %rem.i, %mul.1.i
329  %div.2.i = udiv i64 %rem.1.i, %x
330  %rem.2.i = urem i64 %rem.1.i, %x
331  %mul.i = mul i64 %x, %div.i
332  %add.i = add i64 %mul.i, %div.1.i
333  %mul.1.i9 = mul i64 %add.i, %x
334  %add.1.i = add i64 %mul.1.i9, %div.2.i
335  %mul.2.i11 = mul i64 %add.1.i, %x
336  %add.2.i = add i64 %mul.2.i11, %rem.2.i
337  %sext.i = shl i64 %add.2.i, 32
338  %conv6.i = ashr i64 %sext.i, 32
339  %gep = getelementptr i64, ptr %dst, i64 %conv6.i
340  store i64 %div.i, ptr %gep, align 4
341  %iv.next = add i64 %iv, 1
342  %exitcond.not = icmp eq i64 %iv, %N
343  br i1 %exitcond.not, label %exit, label %loop
344
345exit:
346  ret void
347}
348
349;.
350; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
351; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
352; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
353; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
354; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
355; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
356; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
357; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}
358;.
359