1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -passes=loop-reduce -S %s | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8" 5 6define i32 @btc_0(ptr %a0) { 7; CHECK-LABEL: define i32 @btc_0( 8; CHECK-SAME: ptr [[A0:%.*]]) { 9; CHECK-NEXT: entry: 10; CHECK-NEXT: br label [[LOOP:%.*]] 11; CHECK: loop: 12; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 1, [[ENTRY:%.*]] ] 13; CHECK-NEXT: [[V1:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[V8:%.*]], [[LOOP]] ] 14; CHECK-NEXT: [[V2:%.*]] = load i32, ptr [[A0]], align 4 15; CHECK-NEXT: [[V3:%.*]] = add nsw i32 [[V1]], 1 16; CHECK-NEXT: [[V4:%.*]] = srem i32 [[V2]], 3 17; CHECK-NEXT: [[V5:%.*]] = icmp ne i32 [[V4]], 0 18; CHECK-NEXT: [[V6:%.*]] = sub nsw i32 0, [[V2]] 19; CHECK-NEXT: [[V7:%.*]] = select i1 [[V5]], i32 [[V6]], i32 [[V2]] 20; CHECK-NEXT: [[V8]] = mul nsw i32 [[V3]], [[V7]] 21; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1 22; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0 23; CHECK-NEXT: br i1 [[EC]], label [[B2:%.*]], label [[LOOP]] 24; CHECK: b2: 25; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[V8]], [[LOOP]] ] 26; CHECK-NEXT: br label [[EXIT:%.*]] 27; CHECK: exit: 28; CHECK-NEXT: ret i32 [[RES]] 29; 30entry: 31 br label %loop 32 33loop: 34 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 35 %v1 = phi i32 [ 0, %entry ], [ %v8, %loop ] 36 %v2 = load i32, ptr %a0, align 4 37 %v3 = add nsw i32 %v1, 1 38 %v4 = srem i32 %v2, 3 39 %v5 = icmp ne i32 %v4, 0 40 %v6 = sub nsw i32 0, %v2 41 %v7 = select i1 %v5, i32 %v6, i32 %v2 42 %v8 = mul nsw i32 %v3, %v7 43 %iv.next = add nsw i32 %iv, 1 44 %ec = icmp eq i32 %iv.next, 1 45 br i1 %ec, label %b2, label %loop 46 47b2: 48 %res = phi i32 [ %v8, %loop ] 49 br label %exit 50 51exit: 52 ret i32 %res 53} 54